diff --git a/sw/src/pace/pace_pkg.vhd b/sw/src/pace/pace_pkg.vhd
index f61a8ed..5e177ca 100644
--- a/sw/src/pace/pace_pkg.vhd
+++ b/sw/src/pace/pace_pkg.vhd
@@ -34,6 +34,9 @@ package pace_pkg is
     PACE_TARGET_CARTEBLANCHE_500,
     PACE_TARGET_BEMICRO,
     PACE_TARGET_OPENEP3C16,
+	PACE_TARGET_MIST,
+	PACE_TARGET_CHAMELEON64,
+	PACE_TARGET_RETRORAMBLINGS_CYC3,  -- Generic EP3C25 board with custom io boards
     PACE_TARGET_S5A_R2_EP4C,
     PACE_TARGET_S5A_R2_EP3SL,
     PACE_TARGET_S5A_R2B0_EP4C,
@@ -41,7 +44,7 @@ package pace_pkg is
     PACE_TARGET_S5A_R2C0_EP4C,
     PACE_TARGET_S5A_R2C0_EP3SL,
     PACE_TARGET_S5L_A0_EP4C,
-    PACE_TARGET_S5L_A0_EP3SL,
+    PACE_TARGET_S5L_A0_EP3SL,
     PACE_TARGET_NAVICO_ROCKY
   );
 
diff --git a/sw/src/platform/pacman/altera_mem.vhd b/sw/src/platform/pacman/altera_mem.vhd
index 117fd7b..f035254 100644
--- a/sw/src/platform/pacman/altera_mem.vhd
+++ b/sw/src/platform/pacman/altera_mem.vhd
@@ -18,7 +18,7 @@ begin
 		generic map
 		(
 			init_file		=> "../../../../src/platform/pacman/roms/pacrom.hex",
-			numwords_a	=> 16384,
+--			numwords_a	=> 16384,
 			widthad_a		=> 14
 		)
 		port map
@@ -56,7 +56,7 @@ begin
 		generic map
 		(
 			init_file		=> "../../../../src/platform/pacman/roms/pacvram.hex",
-			numwords_a	=> 1024,
+--			numwords_a	=> 1024,
 			widthad_a		=> 10
 		)
 		port map
@@ -102,7 +102,7 @@ begin
 	dpram_inst : entity work.dpram
 		generic map
 		(
-			numwords_a	=> 1024,
+--			numwords_a	=> 1024,
 			widthad_a		=> 10
 		)
 		port map
@@ -142,7 +142,7 @@ begin
 		generic map
 		(
 			init_file		=> "../../../../src/platform/pacman/roms/pactile.hex",
-			numwords_a	=> 4096,
+--			numwords_a	=> 4096,
 			widthad_a		=> 12
 		)
 		port map
@@ -174,7 +174,7 @@ begin
 		generic map
 		(
 			init_file		=> "../../../../src/platform/pacman/roms/pacsprite32.hex",
-			numwords_a	=> 1024,
+--			numwords_a	=> 1024,
 			widthad_a		=> 10,
 			width_a			=> 32
 		)
@@ -207,7 +207,7 @@ begin
 	spram_inst : entity work.spram
 		generic map
 		(
-			numwords_a => 1024,
+--			numwords_a => 1024,
 			widthad_a => 10
 		)
 		port map
@@ -241,7 +241,7 @@ begin
     generic map
     (
 			init_file		=> SOUND_ROM_INIT_FILE,
-			numwords_a	=> 256,
+--			numwords_a	=> 256,
 			widthad_a		=> 8
     )
     port map
diff --git a/sw/src/target/chameleon64/chameleon_1khz.vhd b/sw/src/target/chameleon64/chameleon_1khz.vhd
new file mode 100644
index 0000000..4b19ee0
--- /dev/null
+++ b/sw/src/target/chameleon64/chameleon_1khz.vhd
@@ -0,0 +1,73 @@
+-- -----------------------------------------------------------------------
+--
+-- Turbo Chameleon
+--
+-- Multi purpose FPGA expansion for the Commodore 64 computer
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/chameleon.html
+--
+-- This source file is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-- -----------------------------------------------------------------------
+--
+-- 1 Khz clock source
+--
+-- -----------------------------------------------------------------------
+-- clk      - system clock input
+-- ena_1mhz - 1 Mhz input, signal must be one cycle high each micro-second.
+-- ena_1khz - 1 Khz output. Signal is one cycle '1' each 1 millisecond.
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- -----------------------------------------------------------------------
+
+entity chameleon_1khz is
+	port (
+		clk : in std_logic;
+		ena_1mhz : in std_logic;
+
+		ena_1khz : out std_logic
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of chameleon_1khz is
+	constant maxcount : integer := 999;
+	signal cnt : integer range 0 to maxcount := maxcount;
+
+	signal ena_out : std_logic := '0';
+begin
+	ena_1khz <= ena_out;
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			ena_out <= '0';
+			if ena_1mhz = '1' then
+				if cnt = 0 then
+					cnt <= maxcount;
+					ena_out <= '1';
+				else
+					cnt <= cnt - 1;
+				end if;
+			end if;
+		end if;
+	end process;
+end architecture;
diff --git a/sw/src/target/chameleon64/chameleon_1mhz.vhd b/sw/src/target/chameleon64/chameleon_1mhz.vhd
new file mode 100644
index 0000000..1f9796d
--- /dev/null
+++ b/sw/src/target/chameleon64/chameleon_1mhz.vhd
@@ -0,0 +1,85 @@
+-- -----------------------------------------------------------------------
+--
+-- Turbo Chameleon
+--
+-- Multi purpose FPGA expansion for the Commodore 64 computer
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/chameleon.html
+--
+-- This source file is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-- -----------------------------------------------------------------------
+--
+-- 1 Mhz clock source
+--
+-- -----------------------------------------------------------------------
+-- clk      - system clock input
+-- ena_1mhz - 1 Mhz output. Signal is one cycle '1' each micro-second.
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- -----------------------------------------------------------------------
+
+entity chameleon_1mhz is
+	generic (
+		-- Timer calibration. Clock speed in Mhz.
+		clk_ticks_per_usec : integer
+	);
+	port (
+		clk : in std_logic;
+
+		ena_1mhz : out std_logic;
+		ena_1mhz_2 : out std_logic
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of chameleon_1mhz is
+	constant maxcount : integer := clk_ticks_per_usec-1;
+	signal cnt : integer range 0 to maxcount := maxcount;
+	signal ena_out : std_logic := '0';
+	signal ena2_out : std_logic := '0';
+begin
+	ena_1mhz <= ena_out;
+	ena_1mhz_2 <= ena2_out;
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			ena_out <= '0';
+			if cnt = 0 then
+				cnt <= maxcount;
+				ena_out <= '1';
+			else
+				cnt <= cnt - 1;
+			end if;
+		end if;
+	end process;
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			ena2_out <= '0';
+			if cnt = (maxcount / 2) then
+				ena2_out <= '1';
+			end if;
+		end if;
+	end process;
+end architecture;
diff --git a/sw/src/target/chameleon64/chameleon_buttons.vhd b/sw/src/target/chameleon64/chameleon_buttons.vhd
new file mode 100644
index 0000000..21bbf22
--- /dev/null
+++ b/sw/src/target/chameleon64/chameleon_buttons.vhd
@@ -0,0 +1,242 @@
+-- -----------------------------------------------------------------------
+--
+-- Turbo Chameleon
+--
+-- Multi purpose FPGA expansion for the Commodore 64 computer
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- http://www.syntiac.com/chameleon.html
+-- -----------------------------------------------------------------------
+--
+-- buttons
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- -----------------------------------------------------------------------
+
+entity chameleon_buttons is
+	generic (
+		shortpress_ms : integer := 50;
+		longpress_ms : integer := 1000
+	);
+	port (
+		clk : in std_logic;
+		clk_1khz : in std_logic;
+		menu_mode : in std_logic;
+		
+		button_l : in std_logic;
+		button_m : in std_logic;
+		button_r : in std_logic;
+		button_l_2 : in std_logic;
+		button_m_2 : in std_logic;
+		button_r_2 : in std_logic;
+		button_config : in unsigned(3 downto 0);
+		
+		reset : out std_logic;
+		boot : out std_logic;
+		freeze : out std_logic;
+		menu : out std_logic;
+		turbo_toggle : out std_logic;
+		disk8_next : out std_logic;
+		disk8_first : out std_logic;
+		disk9_next : out std_logic;
+		disk9_first : out std_logic;
+		cart_toggle : out std_logic;
+		cart_prg : out std_logic;
+		
+		key_up : out std_logic;
+		key_return : out std_logic;
+		key_down : out std_logic
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of chameleon_buttons is
+	signal button_l_cnt : integer range 0 to longpress_ms := 0;
+	signal button_l_long : std_logic := '0';
+	signal button_l_short : std_logic := '0';
+	signal button_m_cnt : integer range 0 to longpress_ms := 0;
+	signal button_m_long : std_logic := '0';
+	signal button_m_short : std_logic := '0';
+	signal button_r_cnt : integer range 0 to longpress_ms := 0;
+	signal button_r_long : std_logic := '0';
+	signal button_r_short : std_logic := '0';
+	
+	signal button_l_dly1 : std_logic := '0';
+	signal button_l_dly2 : std_logic := '0';
+	signal button_l_loc : std_logic := '0';
+	signal button_m_dly1 : std_logic := '0';
+	signal button_m_dly2 : std_logic := '0';
+	signal button_m_loc : std_logic := '0';
+	signal button_r_dly1 : std_logic := '0';
+	signal button_r_dly2 : std_logic := '0';
+	signal button_r_loc : std_logic := '0';
+	
+	signal reset_reg : std_logic := '0';
+	signal boot_reg : std_logic := '0';
+	signal freeze_reg : std_logic := '0';
+	signal menu_reg : std_logic := '0';
+	signal cart_toggle_reg : std_logic := '0';
+	signal cart_prg_reg : std_logic := '0';
+	signal turbo_reg : std_logic := '0';
+	signal disk8_next_reg : std_logic := '0';
+	signal disk8_first_reg : std_logic := '0';
+	signal disk9_next_reg : std_logic := '0';
+	signal disk9_first_reg : std_logic := '0';
+begin
+	reset <= reset_reg;
+	boot <= boot_reg;
+	freeze <= freeze_reg;
+	menu <= menu_reg;
+	
+	turbo_toggle <= turbo_reg;
+	disk8_next <= disk8_next_reg;
+	disk8_first <= disk8_first_reg;
+	disk9_next <= disk9_next_reg;
+	disk9_first <= disk9_first_reg;
+	
+	cart_toggle <= cart_toggle_reg;
+	cart_prg <= cart_prg_reg;
+
+	-- Syncronise buttons to clock (double registered for async inputs)
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			button_l_dly1 <= button_l;
+			button_l_dly2 <= button_l_dly1;
+			button_l_loc <= button_l_dly2 or button_l_2;
+			button_m_dly1 <= button_m;
+			button_m_dly2 <= button_m_dly1;
+			button_m_loc <= button_m_dly2 or button_m_2;
+			button_r_dly1 <= button_r;
+			button_r_dly2 <= button_r_dly1;
+			button_r_loc <= button_r_dly2 or button_r_2;
+		end if;
+	end process;
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			button_l_long <= '0';
+			button_l_short <= '0';
+			if button_l_loc = '1' then
+				if button_l_cnt /= longpress_ms then
+					if clk_1khz = '1' then
+						button_l_cnt <= button_l_cnt + 1;
+					end if;
+					if button_l_cnt > shortpress_ms then
+						button_l_short <= '1';
+					end if;
+				else
+					button_l_long <= '1';
+				end if;
+			else
+				button_l_cnt <= 0;
+			end if;
+		end if;	
+	end process;
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			button_m_long <= '0';
+			button_m_short <= '0';
+			if button_m_loc = '1' then
+				if button_m_cnt /= longpress_ms then
+					if clk_1khz = '1' then
+						button_m_cnt <= button_m_cnt + 1;
+					end if;
+					if button_m_cnt > shortpress_ms then
+						button_m_short <= '1';
+					end if;
+				else
+					button_m_long <= '1';
+				end if;
+			else
+				button_m_cnt <= 0;
+			end if;
+		end if;	
+	end process;
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			button_r_long <= '0';
+			button_r_short <= '0';
+			if button_r_loc = '1' then
+				if button_r_cnt /= longpress_ms then
+					if clk_1khz = '1' then
+						button_r_cnt <= button_r_cnt + 1;
+					end if;
+					if button_r_cnt > shortpress_ms then
+						button_r_short <= '1';
+					end if;
+				else
+					button_r_long <= '1';
+				end if;
+			else
+				button_r_cnt <= 0;
+			end if;
+		end if;	
+	end process;
+
+	
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			reset_reg <= '0';
+			menu_reg <= '0';
+			boot_reg <= '0';
+			cart_toggle_reg <= '0';
+			cart_prg_reg <= '0';
+			turbo_reg <= '0';
+			disk8_next_reg <= '0';
+			disk8_first_reg <= '0';
+			disk9_next_reg <= '0';
+			disk9_first_reg <= '0';
+			if button_l_loc = '0' then
+				if menu_mode = '0' then
+					case button_config is
+					when "0000" =>
+						menu_reg <= button_l_short;
+					when "0001" =>
+						cart_toggle_reg <= button_l_short;
+						cart_prg_reg <= button_l_long;
+					when "0010" =>
+						turbo_reg <= button_l_short;
+					when "0100" =>
+						disk8_next_reg <= button_l_short;
+						disk8_first_reg <= button_l_long;
+					when "0101" =>
+						disk9_next_reg <= button_l_short;
+						disk9_first_reg <= button_l_long;
+					when others =>
+						null;
+					end case;
+				end if;
+			end if;
+			if button_m_loc = '0' then
+				if menu_mode = '0' then
+					freeze_reg <= button_m_short;
+					if button_m_long = '1' then
+						menu_reg <= '1';
+					end if;
+				end if;
+			end if;
+			if button_r_loc = '0' then
+				if menu_mode = '0' then
+					reset_reg <= button_r_short;
+				end if;
+				boot_reg <= button_r_long;
+			end if;
+		end if;	
+	end process;
+end architecture;
diff --git a/sw/src/target/chameleon64/chameleon_c64_joykeyb.vhd b/sw/src/target/chameleon64/chameleon_c64_joykeyb.vhd
new file mode 100644
index 0000000..60d3c1e
--- /dev/null
+++ b/sw/src/target/chameleon64/chameleon_c64_joykeyb.vhd
@@ -0,0 +1,244 @@
+-- -----------------------------------------------------------------------
+--
+-- Turbo Chameleon
+--
+-- Multi purpose FPGA expansion for the Commodore 64 computer
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2013 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com
+--
+-- This source file is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-- -----------------------------------------------------------------------
+--
+-- Keyboard/joystick readout in cartridge mode
+--
+-- -----------------------------------------------------------------------
+-- clk             - system clock
+-- ena_1mhz        - Enable must be '1' one clk cycle each 1 Mhz.
+--
+-- joystick*       - Joystick outputs (fire1, right, left, down, up) low active
+-- keys            - State of the keyboard (low is pressed)
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- -----------------------------------------------------------------------
+
+entity chameleon_c64_joykeyb is
+	generic (
+		enable_4player : boolean
+	);
+	port (
+		clk : in std_logic;
+		ena_1mhz : in std_logic;
+		no_clock : in std_logic;
+		reset : in std_logic;
+		
+		-- To C64 cartridge logic
+		ba : in std_logic;
+		req : out std_logic;
+		ack : in std_logic;
+		we : out std_logic;
+		a : out unsigned(15 downto 0);
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+		
+		joystick1 : out unsigned(4 downto 0);
+		joystick2 : out unsigned(4 downto 0);
+		joystick3 : out unsigned(4 downto 0);
+		joystick4 : out unsigned(4 downto 0);
+		--  0 = col0, row0
+		--  1 = col1, row0
+		--  8 = col0, row1
+		-- 63 = col7, row7
+		keys : out unsigned(63 downto 0)
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of chameleon_c64_joykeyb is
+	type state_t is (
+		INIT_RESET, INIT_DISABLE_VIC, INIT_DISABLE_MOB,
+		INIT_CIA1_A, INIT_CIA1_B, INIT_CIA2_B, --INIT_CIA2_A, ,
+		SET_COL, READ_ROW, STORE_ROW, SET_NOCOL,
+		READ_JOY1, STORE_JOY1, STORE_JOY2,
+		READ_JOY34, STORE_JOY34);
+	signal state : state_t := INIT_RESET;
+	signal req_reg : std_logic := '0';
+	signal joy34_flag : std_logic := '0';
+	signal cnt : unsigned(3 downto 0) := (others => '0');
+	signal col : integer range 0 to 7 := 0;
+	signal keys_reg : unsigned(63 downto 0) := (others => '1');
+begin
+	keys <= keys_reg;
+	req <= req_reg;
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if ena_1mhz = '1' then
+				cnt <= cnt - 1;
+				if cnt = 0 then
+					cnt <= (others => '0');
+				end if;
+			end if;
+			if (req_reg = ack) and (ba = '1') and (cnt = 0) then
+				we <= '-';
+				a <= (others => '-');
+				q <= (others => '-');
+				case state is
+				when INIT_RESET =>
+					if (reset = '0') and (ba = '1') then
+						state <= INIT_DISABLE_VIC;
+					end if;
+				when INIT_DISABLE_VIC =>
+					-- Turn off VIC-II raster DMA, so we don't have to deal with BA.
+					we <= '1';
+					a <= X"D011";
+					q <= X"00";
+					req_reg <= not req_reg;
+					state <= INIT_DISABLE_MOB;
+				when INIT_DISABLE_MOB =>
+					-- Turn off VIC-II sprite DMA, so we don't have to deal with BA.
+					we <= '1';
+					a <= X"D015";
+					q <= X"00";
+					req_reg <= not req_reg;
+					state <= INIT_CIA1_A;
+				when INIT_CIA1_A =>
+					-- Set keyboard columns port (joy2) to output
+					we <= '1';
+					a <= X"DC02";
+					q <= X"FF";
+					req_reg <= not req_reg;
+					state <= INIT_CIA1_B;
+				when INIT_CIA1_B =>
+					-- Set keyboard rows port (joy1) to input
+					we <= '1';
+					a <= X"DC03";
+					q <= X"00";
+					req_reg <= not req_reg;
+					state <= SET_COL;
+					if enable_4player then
+						state <= INIT_CIA2_B;
+					end if;
+				when INIT_CIA2_B =>
+					-- Set CIA2 port B for 4 player adapter
+					-- Bit7 output and others input.
+					we <= '1';
+					a <= X"DD03";
+					q <= X"80";
+					req_reg <= not req_reg;
+					state <= SET_COL;
+				when SET_COL =>
+					we <= '1';
+					a <= X"DC00";
+					q <= to_unsigned(255 - 2**col, 8);
+					req_reg <= not req_reg;
+					cnt <= (others => '1');
+					state <= READ_ROW;
+				when READ_ROW =>
+					we <= '0';
+					a <= X"DC01";
+					req_reg <= not req_reg;
+					state <= STORE_ROW;
+				when STORE_ROW =>
+					keys_reg(0 + col) <= d(0);
+					keys_reg(8 + col) <= d(1);
+					keys_reg(16 + col) <= d(2);
+					keys_reg(24 + col) <= d(3);
+					keys_reg(32 + col) <= d(4);
+					keys_reg(40 + col) <= d(5);
+					keys_reg(48 + col) <= d(6);
+					keys_reg(56 + col) <= d(7);
+					if col /= 7 then
+						col <= col + 1;
+						state <= SET_COL;
+					else
+						col <= 0;
+						state <= SET_NOCOL;
+					end if;
+				when SET_NOCOL =>
+					we <= '1';
+					a <= X"DC00";
+					q <= X"FF";
+					req_reg <= not req_reg;
+					cnt <= (others => '1');
+					state <= READ_JOY1;
+				when READ_JOY1 =>
+					-- read joystick port 1
+					we <= '0';
+					a <= X"DC01";
+					req_reg <= not req_reg;
+					state <= STORE_JOY1;
+				when STORE_JOY1 =>
+					-- read joystick port 2
+					we <= '0';
+					a <= X"DC00";
+					req_reg <= not req_reg;
+					joystick1 <= d(4 downto 0);
+					state <= STORE_JOY2;
+				when STORE_JOY2 =>
+					joystick2 <= d(4 downto 0);
+					state <= SET_COL;
+					if enable_4player then
+						state <= READ_JOY34;
+					end if;
+				when READ_JOY34 =>
+					-- read user port for joystick 3 or 4
+					we <= '0';
+					a <= X"DD01";
+					req_reg <= not req_reg;
+					state <= STORE_JOY34;
+				when STORE_JOY34 =>
+					joystick3(4) <= d(5);
+					joystick4(4) <= d(4);
+					if joy34_flag = '0' then
+						joystick4(3 downto 0) <= d(3 downto 0);
+					else
+						joystick3(3 downto 0) <= d(3 downto 0);
+					end if;
+					-- select the other joystick (3 or 4) on the userport
+					we <= '1';
+					a <= X"DD01";
+					q <= joy34_flag & "0000000";
+					joy34_flag <= not joy34_flag;
+					req_reg <= not req_reg;
+					state <= SET_COL;
+				end case;
+			end if;
+			if reset = '1' then
+				state <= INIT_RESET;
+			end if;
+			if no_clock = '1' then
+				joystick1 <= (others => '1');
+				joystick2 <= (others => '1');
+				joystick3 <= (others => '1');
+				joystick4 <= (others => '1');
+				keys_reg <= (others => '1');
+			end if;
+			if not enable_4player then
+				joystick3 <= (others => '1');
+				joystick4 <= (others => '1');
+			end if;
+		end if;
+	end process;
+end architecture;
+
+
diff --git a/sw/src/target/chameleon64/chameleon_cdtv_remote.vhd b/sw/src/target/chameleon64/chameleon_cdtv_remote.vhd
new file mode 100644
index 0000000..4521675
--- /dev/null
+++ b/sw/src/target/chameleon64/chameleon_cdtv_remote.vhd
@@ -0,0 +1,278 @@
+-- -----------------------------------------------------------------------
+--
+-- Turbo Chameleon
+--
+-- Multi purpose FPGA expansion for the Commodore 64 computer
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/chameleon.html
+--
+-- This source file is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-- -----------------------------------------------------------------------
+--
+-- CDTV IR remote
+--
+-- -----------------------------------------------------------------------
+-- clk         - system clock input
+-- ena_1mhz    - Enable must be '1' one clk cycle each 1 Mhz.
+-- ir          - signal from infra-red detector.
+--
+-- key_1       - high when "1" is pressed on remote
+-- key_2       - high when "2" is pressed on remote
+-- key_3       - high when "3" is pressed on remote
+-- key_4       - high when "4" is pressed on remote
+-- key_5       - high when "5" is pressed on remote
+-- key_6       - high when "6" is pressed on remote
+-- key_7       - high when "7" is pressed on remote
+-- key_8       - high when "8" is pressed on remote
+-- key_9       - high when "9" is pressed on remote
+-- key_0       - high when "0" is pressed on remote
+-- key_escape  - high when "ESCAPE" is pressed on remote
+-- key_enter   - high when "ENTER" is pressed on remote
+-- key_genlock - high when "GENLOCK" is pressed on remote
+-- key_cdtv    - high when "CD/TV" is pressed on remote
+-- key_power   - high when "POWER" is pressed on remote
+-- key_rew     - high when "REW" is pressed on remote
+-- key_play    - high when "PLAY/PAUSE" is pressed on remote
+-- key_ff      - high when "FF" is pressed on remote
+-- key_stop    - high when "STOP" is pressed on remote
+-- key_vol_up  - high when "VOL up" is pressed on remote
+-- key_vol_dn  - high when "VOL dn" is pressed on remote
+-- joystick_a  - first joystick emulation output (bits are '1' when idle).
+--               This output is active when remote is in MOUSE mode.
+-- joystick_b  - second joystick emulation output (bits are '1' when idle).
+--               This output is active when remote is in JOY mode.
+-- debug_code  - Current ir code active
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- -----------------------------------------------------------------------
+
+entity chameleon_cdtv_remote is
+	port (
+		clk : in std_logic;
+		ena_1mhz : in std_logic;
+		ir : in std_logic := '1';
+		
+		trigger : out std_logic;
+
+		key_1 : out std_logic;
+		key_2 : out std_logic;
+		key_3 : out std_logic;
+		key_4 : out std_logic;
+		key_5 : out std_logic;
+		key_6 : out std_logic;
+		key_7 : out std_logic;
+		key_8 : out std_logic;
+		key_9 : out std_logic;
+		key_0 : out std_logic;
+		key_escape : out std_logic;
+		key_enter : out std_logic;
+		key_genlock : out std_logic;
+		key_cdtv : out std_logic;
+		key_power : out std_logic;
+		key_rew : out std_logic;
+		key_play : out std_logic;
+		key_ff : out std_logic;
+		key_stop : out std_logic;
+		key_vol_up : out std_logic;
+		key_vol_dn : out std_logic;
+		joystick_a : out unsigned(5 downto 0);
+		joystick_b : out unsigned(5 downto 0);
+		
+		debug_code : out unsigned(11 downto 0)
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of chameleon_cdtv_remote is
+	constant long_timeout  : integer := 110000; -- 110 msec, this timeout is used while receiving a code (timeout is extended)
+	constant short_timeout : integer :=  75000; --  75 msec, this timeout is used while waiting
+	type state_t is (
+		STATE_IDLE,         -- Nothing received
+		STATE_END_CODE,     -- Code received, reseting timeouts
+		STATE_WAIT_REPEAT,  -- Waiting for new code or key-held code (for 75 ms)
+		STATE_START,        -- Start of new code
+		STATE_LOW,          -- receive ir signal is low
+		STATE_HIGH          -- receive ir signal is high
+		);
+	signal state : state_t := STATE_IDLE;
+	
+	signal pre_trigger : std_logic := '0'; -- trigger out 1 clock later to sync with decoding logic
+	signal timer : integer range 0 to long_timeout := 0;
+	signal bitlength : integer range 0 to 16000 := 0;
+	signal bitcount : integer range 0 to 24 := 0;
+	signal shiftreg : unsigned(23 downto 0) := (others => '0');
+	signal current_code : unsigned(11 downto 0) := (others => '1');
+begin
+	debug_code <= current_code;
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			pre_trigger <= '0';
+		-- State machine
+			case state is
+			when STATE_IDLE =>
+				if (ir = '1') and (bitlength > 8500) then
+					state <= STATE_START;
+				end if;
+				bitcount <= 0;
+			when STATE_END_CODE =>
+				-- Transient state to reset timer.
+				-- Wait for next repeat or new code until timeout.
+				state <= STATE_WAIT_REPEAT;
+				bitcount <= 0;
+			when STATE_WAIT_REPEAT =>
+				if (ir = '1') and (bitlength > 8500) then
+					state <= STATE_START;
+				end if;
+				bitcount <= 0;
+			when STATE_START =>
+				if (ir = '0') and (bitlength > 1500) and (bitlength < 3000) then
+					-- It is a key-held code. No further processing.
+					state <= STATE_END_CODE;
+				end if;
+				if (ir = '0') and (bitlength >= 3000) then
+					state <= STATE_LOW;
+				end if;
+				bitcount <= 0;
+			when STATE_LOW =>
+				if ir = '1' then
+					state <= STATE_HIGH;
+				end if;
+				if bitcount = 24 then
+					state <= STATE_END_CODE;
+					if shiftreg(23 downto 12) = (not shiftreg(11 downto 0)) then
+						-- Valid code
+						current_code <= shiftreg(23 downto 12);
+						pre_trigger <= '1';
+					end if;
+				end if;
+			when STATE_HIGH =>
+				if ir = '0' then
+					state <= STATE_LOW;
+					bitcount <= bitcount + 1;
+					if bitlength > 800 then
+						-- Long bit (1100)
+						shiftreg <= shiftreg(shiftreg'high-1 downto shiftreg'low) & '1';
+					else
+						-- short bit (420)
+						shiftreg <= shiftreg(shiftreg'high-1 downto shiftreg'low) & '0';
+					end if;
+				end if;
+			end case;
+
+		-- Determine bit-length
+			if (ir = '1' and ((state = STATE_IDLE) or (state = STATE_WAIT_REPEAT) or (state = STATE_LOW)))
+			or (ir = '0' and ((state = STATE_START) or (state = STATE_HIGH))) then
+				bitlength <= 0;
+			elsif ena_1mhz = '1' then
+				bitlength <= bitlength + 1;
+			end if;
+
+		-- Process timeout
+			if (state = STATE_IDLE) or (state = STATE_END_CODE) then
+				timer <= 0;
+			elsif timer = long_timeout then
+				-- Timeout occured, reset statemachine
+				state <= STATE_IDLE;
+				bitlength <= 0;
+				current_code <= (others => '1');
+			elsif (timer >= short_timeout) and (state = STATE_WAIT_REPEAT) then
+				-- Timeout occured, reset statemachine
+				state <= STATE_IDLE;
+				bitlength <= 0;
+				current_code <= (others => '1');
+			elsif ena_1mhz = '1' then
+				timer <= timer + 1;
+			end if;
+		end if;
+	end process;
+
+	decode_ir_code: process(clk)
+	begin
+		if rising_edge(clk) then
+			trigger <= pre_trigger;
+			key_1 <= '0';
+			key_2 <= '0';
+			key_3 <= '0';
+			key_4 <= '0';
+			key_5 <= '0';
+			key_6 <= '0';
+			key_7 <= '0';
+			key_8 <= '0';
+			key_9 <= '0';
+			key_0 <= '0';
+			key_escape <= '0';
+			key_enter <= '0';
+			key_genlock <= '0';
+			key_cdtv <= '0';
+			key_power <= '0';
+			key_rew <= '0';
+			key_play <= '0';
+			key_ff <= '0';
+			key_stop <= '0';
+			key_vol_up <= '0';
+			key_vol_dn <= '0';
+			joystick_a <= (others => '1');
+			joystick_b <= (others => '1');
+			
+			case current_code(5 downto 0) is
+			when "000001" => key_1 <= '1';
+			when "100001" => key_2 <= '1';
+			when "010001" => key_3 <= '1';
+			when "001001" => key_4 <= '1';
+			when "101001" => key_5 <= '1';
+			when "011001" => key_6 <= '1';
+			when "000101" => key_7 <= '1';
+			when "100101" => key_8 <= '1';
+			when "010101" => key_9 <= '1';
+			when "111001" => key_0 <= '1';
+			when "110001" => key_escape <= '1';
+			when "110101" => key_enter <= '1';
+			when "100010" => key_genlock <= '1';
+			when "000010" => key_cdtv <= '1';
+			when "010010" => key_power <= '1';
+			when "110010" => key_rew <= '1';
+			when "001010" => key_play <= '1';
+			when "011010" => key_ff <= '1';
+			when "101010" => key_stop <= '1';
+			when "000110" => key_vol_up <= '1';
+			when "111010" => key_vol_dn <= '1';
+			when others =>
+				null;
+			end case;
+			
+			if (current_code(11) = '0') and (current_code(1 downto 0) = "00") then
+				joystick_a <= not (current_code(6) & current_code(7) & current_code(2) & current_code(3) & current_code(4) & current_code(5));
+			end if;
+			if (current_code(11) = '1') and (current_code(1 downto 0) = "00") then
+				joystick_b <= not (current_code(6) & current_code(7) & current_code(2) & current_code(3) & current_code(4) & current_code(5));
+			end if;
+		end if;	
+	end process;
+
+end architecture;
+
+
+
+
+
diff --git a/sw/src/target/chameleon64/chameleon_docking_station.vhd b/sw/src/target/chameleon64/chameleon_docking_station.vhd
new file mode 100644
index 0000000..f41c12a
--- /dev/null
+++ b/sw/src/target/chameleon64/chameleon_docking_station.vhd
@@ -0,0 +1,213 @@
+-- -----------------------------------------------------------------------
+--
+-- Turbo Chameleon
+--
+-- Multi purpose FPGA expansion for the Commodore 64 computer
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2012 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- Allowed to be used in your own projects that are targeted for the
+-- Turbo Chameleon 64 cartridge.
+--
+-- http://www.syntiac.com/chameleon.html
+-- -----------------------------------------------------------------------
+--
+-- Chameleon docking station
+--
+-- -----------------------------------------------------------------------
+-- clk             - system clock
+-- docking_station - must be high when docking-station is available.
+--                   This can be determined by the state of the phi2 pin.
+-- dotclock_n      - Connect to the dotclock_n pin.
+-- io_ef_n         - Connect to the io_ef_n pin.
+-- rom_hl_n        - Connect to the rom_hl_n pin.
+-- irq_q           - IRQ pin output (open drain output, 0 is drive low, 1 is input)
+-- joystick*       - Joystick outputs (fire2, fire1, right, left, down, up) low active
+-- keys            - State of the keyboard (low is pressed)
+-- restore_key_n   - State of the restore key (low is pressed)
+--
+-- amiga_power_led - Control input for the POWER LED on the Amiga keyboard.
+-- amiga_drive_led - Control input for the DRIVE LED on the Amiga keyboard.
+-- amiga_reset_n   - Low when the Amiga keyboard does a reset.
+-- amiga_trigger   - One clock high when the Amiga keyboard has send a new scancode.
+-- amiga_scancode  - Value of the last received scancode from the Amiga keyboard.
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- -----------------------------------------------------------------------
+
+entity chameleon_docking_station is
+	port (
+		clk : in std_logic;
+		docking_station : in std_logic;
+
+		dotclock_n : in std_logic;
+		io_ef_n : in std_logic;
+		rom_lh_n : in std_logic;
+		irq_q : out std_logic;
+		
+		joystick1 : out unsigned(5 downto 0);
+		joystick2 : out unsigned(5 downto 0);
+		joystick3 : out unsigned(5 downto 0);
+		joystick4 : out unsigned(5 downto 0);
+		--  0 = col0, row0
+		--  1 = col1, row0
+		--  8 = col0, row1
+		-- 63 = col7, row7
+		keys : out unsigned(63 downto 0);
+		restore_key_n : out std_logic;
+		
+	-- Amiga keyboard
+		amiga_power_led : in std_logic;
+		amiga_drive_led : in std_logic;
+		amiga_reset_n : out std_logic;
+		amiga_trigger : out std_logic;
+		amiga_scancode : out unsigned(7 downto 0)
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of chameleon_docking_station is
+	constant shift_reg_bits : integer := 13*8;
+	-- We put the out-of-sync detection just before the actual sync-pulse.
+	-- Gives it the biggest chance of catching a sync-problem.
+	constant out_of_sync_pos : integer := 102; 
+	signal shift_reg : unsigned(shift_reg_bits-1 downto 0);
+	signal bit_cnt : unsigned(7 downto 0) := (others => '0');
+	signal once : std_logic := '0';
+
+	signal key_reg : unsigned(63 downto 0) := (others => '1');
+	signal restore_n_reg : std_logic := '1';
+	signal joystick1_reg : unsigned(5 downto 0) := (others => '0');
+	signal joystick2_reg : unsigned(5 downto 0) := (others => '0');
+	signal joystick3_reg : unsigned(5 downto 0) := (others => '0');
+	signal joystick4_reg : unsigned(5 downto 0) := (others => '0');
+	signal dotclock_n_reg : std_logic := '0';
+	signal dotclock_n_dly : std_logic := '0';
+	signal io_ef_n_reg : std_logic := '0';
+	signal rom_lh_n_reg : std_logic := '1';
+	signal irq_q_reg : std_logic := '1';
+	
+	signal amiga_reset_n_reg : std_logic := '0';
+	signal amiga_trigger_reg : std_logic := '0';
+	signal amiga_scancode_reg : unsigned(7 downto 0) := (others => '0');
+begin
+	joystick1 <= joystick1_reg;
+	joystick2 <= joystick2_reg;
+	joystick3 <= joystick3_reg;
+	joystick4 <= joystick4_reg;
+	keys <= key_reg;
+	restore_key_n <= restore_n_reg;
+	amiga_reset_n <= amiga_reset_n_reg;
+	amiga_trigger <= amiga_trigger_reg;
+	amiga_scancode <= amiga_scancode_reg;
+	irq_q <= irq_q_reg;
+
+	--
+	-- Sample DotClock, IO_EF and ROM_LH input.
+	process(clk) is
+	begin
+		if rising_edge(clk) then
+			dotclock_n_reg <= dotclock_n;
+			dotclock_n_dly <= dotclock_n_reg;
+			io_ef_n_reg <= io_ef_n;
+			rom_lh_n_reg <= rom_lh_n;
+		end if;
+	end process;
+
+	--
+	-- Receive serial stream
+	process(clk) is
+	begin
+		if rising_edge(clk) then
+			if (dotclock_n_reg = '0') and (dotclock_n_dly = '1') then
+				shift_reg <= (not rom_lh_n_reg) & shift_reg(shift_reg'high downto 1);
+				bit_cnt <= bit_cnt + 1;
+			end if;
+			if (io_ef_n_reg = '1') and (bit_cnt = out_of_sync_pos) then
+				-- Out of sync detection.
+				-- Wait for the MCU on the docking-station to release io_ef
+				-- Then we can continue and syncronise on the next io_ef pulse that comes.
+				bit_cnt <= to_unsigned(out_of_sync_pos, bit_cnt'length);
+			end if;
+			if (io_ef_n_reg = '1') and (bit_cnt >= shift_reg_bits) then
+				-- Word trigger. Signals start of serial bit-stream.
+				bit_cnt <= (others => '0');
+			end if;
+		end if;
+	end process;
+	
+	--
+	-- Amiga keyboard LED control
+	process(clk) is
+	begin
+		if rising_edge(clk) then
+			irq_q_reg <= '1';
+			if (bit_cnt >= 40) and (bit_cnt < 56) then
+				irq_q_reg <= amiga_power_led;
+			end if;
+			if (bit_cnt >= 72) and (bit_cnt < 88) then
+				irq_q_reg <= amiga_drive_led;
+			end if;
+		end if;
+	end process;
+
+	--
+	-- Decode bytes
+	process(clk) is
+	begin
+		if rising_edge(clk) then
+			if bit_cnt = shift_reg_bits then
+				-- Map shifted bits to joysticks
+				joystick1_reg <= shift_reg(101 downto 96);
+				joystick2_reg <= shift_reg(85 downto 80);
+				joystick3_reg <= shift_reg(102)& shift_reg(103) & shift_reg(92) & shift_reg(93) & shift_reg(94) & shift_reg(95);
+				joystick4_reg <= shift_reg(86) & shift_reg(87) & shift_reg(88) & shift_reg(89) & shift_reg(90) & shift_reg(91);
+				restore_n_reg <= shift_reg(1);
+
+				-- Map shifted bits to C64 keyboard
+				if (shift_reg(87 downto 80) = X"FF") and (shift_reg(103 downto 96) = X"FF") then
+					for row in 0 to 7 loop
+						for col in 0 to 7 loop
+							-- uC scans column wise.
+							key_reg(row*8 + col) <= shift_reg(16 + col*8 + row);
+						end loop;
+					end loop;
+				else
+					-- Prevent conflict between keyboard and joystick.
+					-- Relase all keyboard keys while joystick button(s) are pressed.
+					key_reg <= (others => '1');
+				end if;
+				
+				-- Amiga keyboard
+				amiga_reset_n_reg <= shift_reg(2);
+				if shift_reg(0) = '1' then
+					amiga_scancode_reg <= shift_reg(15 downto 8);
+					amiga_trigger_reg <= once;
+				end if;
+				once <= '0';
+			end if;
+			if (io_ef_n_reg = '1') then
+				once <= '1';
+			end if;
+
+			-- No docking station connected.
+			-- Disable all outputs to prevent conflicts.
+			if docking_station = '0' then
+				joystick1_reg <= (others => '1');
+				joystick2_reg <= (others => '1');
+				joystick3_reg <= (others => '1');
+				joystick4_reg <= (others => '1');
+				key_reg <= (others => '1');
+				restore_n_reg <= '1';
+				amiga_reset_n_reg <= '1';
+			end if;
+		end if;
+	end process;
+end architecture;
diff --git a/sw/src/target/chameleon64/chameleon_io.vhd b/sw/src/target/chameleon64/chameleon_io.vhd
new file mode 100644
index 0000000..a6a96e1
--- /dev/null
+++ b/sw/src/target/chameleon64/chameleon_io.vhd
@@ -0,0 +1,918 @@
+-- -----------------------------------------------------------------------
+--
+-- Turbo Chameleon
+--
+-- Multi purpose FPGA expansion for the Commodore 64 computer
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2013 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com
+--
+-- This source file is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-- -----------------------------------------------------------------------
+--
+-- For better understanding what this entity does in detail, please refer
+-- to the Chameleon core-developers manual. It has documentation about
+-- the CPLD MUX, signal timing, docking-station protocol and the cartridge port access.
+--
+-- Chameleon timing and I/O driver. Handles all the timing and multiplexing
+-- details of the cartridge port and the CPLD mux.
+--   - Detects the type of mode the chameleon is running in.
+--   - Multiplexes the PS/2 keyboard and mouse signals.
+--   - Gives access to joysticks and keyboard on a C64 in cartridge mode.
+--   - Gives access to joysticks and keyboard on a docking-station
+--   - Gives access to MMC card and serial-flash through the CPLD MUX.
+--   - Drives the two LEDs on the Chameleon (or an optional Amiga keyboard).
+--   - Can optionally give access to the IEC bus
+--   - Can optionally give access to other C64 resources like the SID.
+--
+-- -----------------------------------------------------------------------
+-- enable_docking_station - Enable support for the docking-station.
+-- enable_c64_joykeyb     - Automatically read joystick and keyboard on the C64 bus.
+--                          Take note this disables the C64 bus access feature on this entity.
+-- enable_c64_4player     - Enable 4player support on the user-port of the C64.
+--                          The flag enable_c64_joykeyb must be true for this to work.
+-- enable_raw_spi         - SPI controller inside this entity is switched off.
+--                          And the actual SPI lines are exposed. The maximum speed is limited
+--                          as the signals are time multiplexed. The maximum spi speed usable
+--                          is around 1/12 of clk. (One line transition each 6 clk cycles)
+-- enable_iec_access      - Enables support for the IEC bus on the break-out cable.
+--                          Set this to 'false' when the IEC bus is not used to save some logic.
+-- -----------------------------------------------------------------------
+-- clk             - system clock
+-- ena_1mhz        - Enable must be '1' one clk cycle each 1 Mhz.
+-- reset           - Perform a reset of the subsystems
+-- reset_ext       - Hardware reset from the cartridge-port (eg. a C64 reset button)
+--
+-- no_clock        - '0' when connected to C64 cartridge port.
+--                   '1' when in standalone mode or docking-station connected.
+-- docking_station - '0' standalone/cartrdige mode
+--                   '1' when docking-station is connected.
+--
+-- to_usb_rx
+--
+-- The following timing signals are only useful when writing C64 related designs.
+-- They can be left unconnected in all other FPGA designs.
+-- phi_mode        - Selects timing in standalone mode ('0' is PAL, '1' is NTSC).
+-- phi_out         - Regenerated or synthesized phi2 clock.
+-- phi_cnt         - Counting the system-clock cycles within one phi2 cycle.
+-- phi_end_0       - The half of the cycle where phi_out is low ends.
+-- phi_end_1       - The half of the cycle where phi_out is high ends.
+-- phi_post_1      - Triggers when phi changes
+-- phi_post_2      - Triggers one cycle after phi changed
+-- phi_post_3      - Triggers two cycles phi changed
+-- phi_post_4      - Triggers three cycles phi changed
+--
+-- c64_irq_n       - Status of the C64 IRQ line (cartridge mode only)
+-- c64_nmi_n       - Status of the C64 NMI line
+-- c64_ba          - status of the C64 BA line
+--
+-- The following signals should be synchronised to the phi_out signal
+-- c64_vic         - When set data on c64_d is send to the VIC-II chip.
+-- c64_cs          - When set it accesses the C64 databus (uses Ultimax mode, no memory is mapped)
+-- c64_cs_roms     - Enables access to the C64 Kernal and Basic ROMs (disables Ultimax mode)
+-- c64_clockport   - When set it accesses the clockport.
+-- c64_we          - Access is a write when set (note polarity is the inverse of R/W on cartridge port)
+-- c64_a           - C64 address bus
+-- c64_d           - Data to the C64
+-- c64_q           - Data from the C64 (only valid when phi_end_1 is set)
+--
+-- spi_speed       - 0 SPI bus runs at slow speed (250 Kbit), SPI bus runs at fast speed (8 Mbit)
+-- spi_req         - Toggle to request SPI transfer.
+-- spi_ack         - Is made equal to spi_req after transfer is complete.
+-- spi_d           - Data input into SPI controller.
+-- spi_q           - Data output from SPI controller.
+--
+-- led_green       - Control the green LED (0 off, 1 on). Also power LED on Amiga keyboard.
+-- led_red         - Control the red LED (0 off, 1 on). Also drive LED on Amiga keyboard.
+-- ir              - ir signal. Input for the chameleon_cdtv_remote entity.
+--
+-- ps2_*           - PS2 signals for both keyboard and mouse.
+-- button_reset_n  - Status of blue reset button (right button) on the Chameleon. Low active.
+-- joystick*       - Joystick ports of both docking-station and C64.  Bits: fire2, fire1, right, left, down, up
+--                   The C64 only supports one button fire1. The signals are low active
+-- keys            - C64 keyboard. One bit for each key on the keyboard. Low active.
+-- restore_key_n   - Trigger for restore key on docking-station.
+--                   On a C64 the restore key is wired to the NMI line instead.
+-- iec_*           - IEC signals. Only valid when enable_iec_access is set to true.
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- -----------------------------------------------------------------------
+
+entity chameleon_io is
+	generic (
+		enable_docking_station : boolean := true;
+		enable_c64_joykeyb : boolean := false;
+		enable_c64_4player : boolean := false;
+		enable_raw_spi : boolean := false;
+		enable_iec_access : boolean := false
+	);
+	port (
+-- Clocks
+		clk : in std_logic;
+		clk_mux : in std_logic;
+		ena_1mhz : in std_logic;
+		reset : in std_logic;
+		reset_ext : out std_logic;
+
+-- Config
+		no_clock : out std_logic;
+		docking_station : out std_logic;
+
+-- Chameleon FPGA pins
+		-- C64 Clocks
+		phi2_n : in std_logic;
+		dotclock_n : in std_logic;
+		-- C64 cartridge control lines
+		io_ef_n : in std_logic;
+		rom_lh_n : in std_logic;
+		-- SPI bus
+		spi_miso : in std_logic;
+		-- CPLD multiplexer
+		mux_clk : out std_logic;
+		mux : out unsigned(3 downto 0);
+		mux_d : out unsigned(3 downto 0);
+		mux_q : in unsigned(3 downto 0);
+
+-- USB microcontroller (To RX of micro)
+		to_usb_rx : in std_logic := '1';
+
+-- C64 timing (only for C64 related cores)
+		phi_mode : in std_logic := '0';
+		phi_out : out std_logic;
+		phi_cnt : out unsigned(7 downto 0);
+		phi_end_0 : out std_logic;
+		phi_end_1 : out std_logic;
+		phi_post_1 : out std_logic;
+		phi_post_2 : out std_logic;
+		phi_post_3 : out std_logic;
+		phi_post_4 : out std_logic;
+
+-- C64 bus
+		c64_irq_n : out std_logic;
+		c64_nmi_n : out std_logic;
+		c64_ba : out std_logic;
+
+		c64_vic : in std_logic := '0';
+		c64_cs : in std_logic := '0';
+		c64_cs_roms : in std_logic := '0';
+		c64_clockport : in std_logic := '0';
+		c64_we : in std_logic := '0';
+		c64_a : in unsigned(15 downto 0) := (others => '0');
+		c64_d : in unsigned(7 downto 0) := (others => '1');
+		c64_q : out unsigned(7 downto 0);
+
+-- SPI chip-selects
+		mmc_cs_n : in std_logic := '1';
+		flash_cs_n : in std_logic := '1';
+		rtc_cs : in std_logic := '0';
+
+-- SPI controller (enable_raw_spi must be set to false)
+		spi_speed : in std_logic := '1';
+		spi_req : in std_logic := '0';
+		spi_ack : out std_logic;
+		spi_d : in unsigned(7 downto 0) := (others => '-');
+		spi_q : out unsigned(7 downto 0);
+
+-- SPI raw signals (enable_raw_spi must be set to true)
+		spi_raw_clk : in std_logic := '1';
+		spi_raw_mosi : in std_logic := '1';
+		spi_raw_ack : out std_logic;  -- Added by AMR
+		
+-- LEDs
+		led_green : in std_logic := '0';
+		led_red : in std_logic := '0';
+		ir : out std_logic;
+
+-- PS/2 Keyboard
+		ps2_keyboard_clk_out: in std_logic := '1';
+		ps2_keyboard_dat_out: in std_logic := '1';
+		ps2_keyboard_clk_in: out std_logic;
+		ps2_keyboard_dat_in: out std_logic;
+
+-- PS/2 Mouse
+		ps2_mouse_clk_out: in std_logic := '1';
+		ps2_mouse_dat_out: in std_logic := '1';
+		ps2_mouse_clk_in: out std_logic;
+		ps2_mouse_dat_in: out std_logic;
+
+-- Buttons
+		button_reset_n : out std_logic;
+		
+-- Joysticks
+		joystick1 : out unsigned(5 downto 0);
+		joystick2 : out unsigned(5 downto 0);
+		joystick3 : out unsigned(5 downto 0);
+		joystick4 : out unsigned(5 downto 0);
+
+-- Keyboards
+		--  0 = col0, row0
+		--  1 = col1, row0
+		--  8 = col0, row1
+		-- 63 = col7, row7
+		keys : out unsigned(63 downto 0);
+		restore_key_n : out std_logic;
+		amiga_reset_n : out std_logic;
+		amiga_trigger : out std_logic;
+		amiga_scancode : out unsigned(7 downto 0);
+
+-- IEC bus
+		iec_clk_out : in std_logic := '1';
+		iec_dat_out : in std_logic := '1';
+		iec_atn_out : in std_logic := '1';
+		iec_srq_out : in std_logic := '1';
+		iec_clk_in : out std_logic;
+		iec_dat_in : out std_logic;
+		iec_atn_in : out std_logic;
+		iec_srq_in : out std_logic
+	);
+end entity;
+-- -----------------------------------------------------------------------
+
+architecture rtl of chameleon_io is
+-- Clocks
+	signal no_clock_loc : std_logic;
+	signal phi : std_logic;
+	signal end_of_phi_0 : std_logic;
+	signal end_of_phi_1 : std_logic;
+	
+-- State
+	signal reset_pending : std_logic := '0';
+	signal reset_in : std_logic := '0';
+
+-- MUX
+	type muxstate_t is (
+		-- Reset phase
+		MUX_RESET,
+		-- MMC
+		MUX_MMC0L, MUX_MMC0H, MUX_MMC1L, MUX_MMC1H, MUX_MMC2L, MUX_MMC2H, MUX_MMC3L, MUX_MMC3H,
+		MUX_MMC4L, MUX_MMC4H, MUX_MMC5L, MUX_MMC5H, MUX_MMC6L, MUX_MMC6H, MUX_MMC7L, MUX_MMC7H,
+		-- IEC
+		MUX_IEC1, MUX_IEC2, MUX_IEC3, MUX_IEC4,
+		-- PS2
+		MUX_PS2,
+		-- LED
+		MUX_LED,
+		-- PHI=0
+		MUX_WAIT0,
+		MUX_A3_C, MUX_BUSVIC,
+		MUX_D0VIC, MUX_D1VIC,
+		MUX_NMIIRQ1, MUX_NMIIRQ2,
+		MUX_ULTIMAX,
+		MUX_END0,
+		-- PHI=1
+		MUX_WAIT1,
+		MUX_BUS, MUX_CLKPORT,
+		MUX_A0, MUX_A1, MUX_A2, MUX_A3,
+		MUX_D0WR, MUX_D1WR, MUX_D0WR_1, MUX_D1WR_1, MUX_D0WR_2, MUX_D1WR_2,
+		MUX_D0RD_1, MUX_D1RD_1, MUX_D0RD_2, MUX_D1RD_2
+	);
+	signal mux_state : muxstate_t;
+	signal mux_toggle : std_logic := '0';
+
+	signal mux_c128_timeout : unsigned(7 downto 0) := (others => '1');
+	signal mux_clk_reg : std_logic := '0';
+	signal mux_d_reg : unsigned(mux_d'range) := X"F";
+	signal mux_reg : unsigned(mux'range) := X"F";
+	signal mux_d_mmc : unsigned(1 downto 0) := "11";
+
+-- C64 bus
+	signal c64_reset_reg : std_logic := '0';
+	signal c64_ba_reg : std_logic := '1';
+	signal c64_data_reg : unsigned(7 downto 0) := (others => '1');
+	signal c64_addr : unsigned(15 downto 0) := (others => '0');
+	signal c64_to_io : unsigned(7 downto 0) := (others => '0');
+	
+	signal c64_we_loc : std_logic := '0';
+	signal c64_vic_loc : std_logic := '0';
+	signal c64_cs_loc : std_logic := '0';
+	signal c64_roms_loc : std_logic := '0';
+	signal c64_clockport_loc : std_logic := '0';
+	
+-- C64 joystick/keyboard
+	signal c64_kb_req : std_logic := '0';
+	signal c64_kb_ack : std_logic := '0';
+	signal c64_kb_we : std_logic := '1';
+	signal c64_kb_a : unsigned(15 downto 0) := (others => '0');
+	signal c64_kb_q : unsigned(7 downto 0) := (others => '1');
+	signal c64_joystick1 : unsigned(4 downto 0);
+	signal c64_joystick2 : unsigned(4 downto 0);
+	signal c64_joystick3 : unsigned(4 downto 0);
+	signal c64_joystick4 : unsigned(4 downto 0);
+	signal c64_keys : unsigned(63 downto 0);
+
+-- Docking-station
+	signal docking_station_loc : std_logic;
+	signal docking_irq : std_logic;
+	signal docking_joystick1 : unsigned(5 downto 0);
+	signal docking_joystick2 : unsigned(5 downto 0);
+	signal docking_joystick3 : unsigned(5 downto 0);
+	signal docking_joystick4 : unsigned(5 downto 0);
+	signal docking_keys : unsigned(63 downto 0);
+	signal docking_amiga_reset_n : std_logic;
+	signal docking_amiga_scancode : unsigned(7 downto 0);
+
+-- MMC
+	signal mmc_state : unsigned(5 downto 0) := (others => '0');
+	signal spi_q_reg : unsigned(7 downto 0) := (others => '1');
+	signal spi_run : std_logic := '0';
+	signal spi_sample : std_logic := '0';
+	signal mmc_shift_req : std_logic;
+	signal mmc_shift_ack : std_logic := '0';
+
+-- IEC
+	signal iec_clk_reg : std_logic := '1';
+	signal iec_dat_reg : std_logic := '1';
+	signal iec_atn_reg : std_logic := '1';
+	signal iec_srq_reg : std_logic := '1';
+begin
+	reset_ext <= reset_in;
+	no_clock <= no_clock_loc;
+	docking_station <= docking_station_loc;
+	--
+	phi_out <= phi;
+	phi_end_0 <= end_of_phi_0;
+	phi_end_1 <= end_of_phi_1;
+	--
+	c64_ba <= c64_ba_reg;
+	c64_q <= c64_data_reg;
+	--
+	spi_q <= spi_q_reg;
+	--
+	joystick1 <= docking_joystick1 and ("1" & c64_joystick1);
+	joystick2 <= docking_joystick2 and ("1" & c64_joystick2);
+	joystick3 <= docking_joystick3 and ("1" & c64_joystick3);
+	joystick4 <= docking_joystick4 and ("1" & c64_joystick4);
+	keys <= docking_keys and c64_keys;
+
+-- -----------------------------------------------------------------------
+-- PHI2 clock sync
+-- -----------------------------------------------------------------------
+	phiInstance : entity work.chameleon_phi_clock
+		port map (
+			clk => clk,
+			phi2_n => phi2_n,
+			mode => phi_mode,
+
+			no_clock => no_clock_loc,
+			docking_station => docking_station_loc,
+
+			phiLocal => phi,
+			phiCnt => phi_cnt,
+			phiPreHalf => end_of_phi_0,
+			phiPreEnd => end_of_phi_1,
+			phiPost1 => phi_post_1,
+			phiPost2 => phi_post_2,
+			phiPost3 => phi_post_3,
+			phiPost4 => phi_post_4
+		);
+
+-- -----------------------------------------------------------------------
+-- Docking-station
+-- To enable set enable_docking_station to true.
+-- -----------------------------------------------------------------------
+	genDockingStation : if enable_docking_station generate
+		myDockingStation : entity work.chameleon_docking_station
+			port map (
+				clk => clk,
+				
+				docking_station => docking_station_loc,
+				
+				dotclock_n => dotclock_n,
+				io_ef_n => io_ef_n,
+				rom_lh_n => rom_lh_n,
+				irq_q => docking_irq,
+				
+				joystick1 => docking_joystick1,
+				joystick2 => docking_joystick2,
+				joystick3 => docking_joystick3,
+				joystick4 => docking_joystick4,
+				keys => docking_keys,
+				restore_key_n => restore_key_n,
+				
+				amiga_power_led => led_green,
+				amiga_drive_led => led_red,
+				amiga_reset_n => amiga_reset_n,
+				amiga_trigger => amiga_trigger,
+				amiga_scancode => amiga_scancode
+			);
+	end generate;
+
+	noDockingStation : if not enable_docking_station generate
+		docking_joystick1 <= (others => '1');
+		docking_joystick2 <= (others => '1');
+		docking_joystick3 <= (others => '1');
+		docking_joystick4 <= (others => '1');
+		docking_keys <= (others => '1');
+	end generate;
+
+-- -----------------------------------------------------------------------
+-- C64 keyboard and joystick support
+-- To enable set enable_c64_joykeyb to true.
+-- -----------------------------------------------------------------------
+	genC64JoyKeyb : if enable_c64_joykeyb generate
+		myC64JoyKeyb : entity work.chameleon_c64_joykeyb
+			generic map (
+				enable_4player => enable_c64_4player
+			)
+			port map (
+				clk => clk,
+				ena_1mhz => ena_1mhz,
+				no_clock => no_clock_loc,
+				reset => reset,
+				
+				ba => c64_ba_reg,
+				req => c64_kb_req,
+				ack => c64_kb_ack,
+				we => c64_kb_we,
+				a => c64_kb_a,
+				d => c64_data_reg,
+				q => c64_kb_q,
+				
+				joystick1 => c64_joystick1,
+				joystick2 => c64_joystick2,
+				joystick3 => c64_joystick3,
+				joystick4 => c64_joystick4,
+				keys => c64_keys
+			);
+
+		c64_addr <= c64_kb_a;
+		c64_to_io <= c64_kb_q;
+		c64_vic_loc <= '0';
+		c64_roms_loc <= '0';
+		c64_clockport_loc <= '0';
+		c64_we_loc <= c64_kb_we;
+
+		process(clk)
+		begin
+			if rising_edge(clk) then
+				if end_of_phi_1 = '1' then
+					c64_cs_loc <= '0';
+					if c64_kb_req /= c64_kb_ack then
+						if c64_cs_loc = '1' then
+							c64_kb_ack <= c64_kb_req;
+						else
+							c64_cs_loc <= '1';
+						end if;
+					end if;
+				end if;
+			end if;
+		end process;
+	end generate;
+	
+	noC64JoyKeyb : if not enable_c64_joykeyb generate
+		c64_joystick1 <= (others => '1');
+		c64_joystick2 <= (others => '1');
+		c64_joystick3 <= (others => '1');
+		c64_joystick4 <= (others => '1');
+		c64_keys <= (others => '1');
+		
+		c64_addr <= c64_a;
+		c64_to_io <= c64_d;
+
+		c64_vic_loc <= c64_vic;
+		c64_cs_loc <= c64_cs;
+		c64_roms_loc <= c64_cs_roms;
+		c64_clockport_loc <= c64_clockport;
+		c64_we_loc <= c64_we;
+	end generate;
+
+-- -----------------------------------------------------------------------
+-- MUX CPLD
+-- -----------------------------------------------------------------------
+	-- MUX clock
+	process(clk_mux)
+	begin
+		if rising_edge(clk_mux) then
+			mux_clk_reg <= not mux_clk_reg;
+		end if;
+	end process;
+
+	-- MUX sequence
+	process(clk_mux)
+	begin
+		if rising_edge(clk_mux) then
+			if mux_clk_reg = '1' then
+				mux_toggle <= not mux_toggle;
+				case mux_state is
+				when MUX_RESET   =>
+					if phi = '1' then
+						mux_state <= MUX_WAIT0;
+					end if;
+-- PHI2  0
+				when MUX_WAIT0   =>
+					if phi = '0' then
+						mux_state <= MUX_MMC0L;
+						if mux_c128_timeout /= 0 then
+							mux_c128_timeout <= mux_c128_timeout - 1;
+						end if;
+					end if;
+				when MUX_MMC0L   => mux_state <= MUX_A3_C;
+				when MUX_A3_C    => mux_state <= MUX_ULTIMAX;
+				when MUX_ULTIMAX => mux_state <= MUX_MMC0H;
+				when MUX_MMC0H   => mux_state <= MUX_BUSVIC;
+				when MUX_BUSVIC  => mux_state <= MUX_IEC1;
+				when MUX_IEC1    => mux_state <= MUX_MMC1L;
+				when MUX_MMC1L   => mux_state <= MUX_PS2;
+				when MUX_PS2     => mux_state <= MUX_A2;
+				when MUX_A2      => mux_state <= MUX_MMC1H;
+				when MUX_MMC1H   => mux_state <= MUX_NMIIRQ1;
+				when MUX_NMIIRQ1 => mux_state <= MUX_LED;
+				when MUX_LED     => mux_state <= MUX_MMC2L;
+				when MUX_MMC2L   => mux_state <= MUX_A0;
+				when MUX_A0      => mux_state <= MUX_IEC4;
+				when MUX_IEC4    => mux_state <= MUX_MMC2H;
+				when MUX_MMC2H   => mux_state <= MUX_A1;
+				when MUX_A1      => mux_state <= MUX_D0VIC;
+				when MUX_D0VIC   => mux_state <= MUX_D1VIC;
+				when MUX_D1VIC   => mux_state <= MUX_MMC3L;
+				when MUX_MMC3L   => mux_state <= MUX_IEC3;
+				when MUX_IEC3    => mux_state <= MUX_MMC3H;
+				when MUX_MMC3H   => mux_state <= MUX_END0;
+				when MUX_END0    => mux_state <= MUX_WAIT1;
+-- PHI2  1
+				when MUX_WAIT1 =>
+					if phi = '1' then
+						mux_state <= MUX_MMC4L;
+					end if;
+				when MUX_MMC4L   => mux_state <= MUX_BUS;
+				when MUX_BUS     => mux_state <= MUX_D0WR;
+				when MUX_D0WR    => mux_state <= MUX_D1WR;
+				when MUX_D1WR    => mux_state <= MUX_MMC4H;
+				when MUX_MMC4H   => mux_state <= MUX_A3;
+				when MUX_A3      => mux_state <= MUX_CLKPORT;
+				when MUX_CLKPORT => mux_state <= MUX_MMC5L;
+				when MUX_MMC5L   => mux_state <= MUX_NMIIRQ2;
+				when MUX_NMIIRQ2 => mux_state <= MUX_MMC5H;
+				when MUX_MMC5H   => mux_state <= MUX_D0WR_1;
+				when MUX_D0WR_1  => mux_state <= MUX_D1WR_1;
+				when MUX_D1WR_1  => mux_state <= MUX_MMC6L;
+				when MUX_MMC6L   => mux_state <= MUX_IEC2;
+				when MUX_IEC2    => mux_state <= MUX_MMC6H;
+				--when MUX_LED     => mux_state <= MUX_MMC6H;
+				when MUX_MMC6H   => mux_state <= MUX_D0WR_2;
+				when MUX_D0WR_2  => mux_state <= MUX_D1WR_2;
+				when MUX_D1WR_2  => mux_state <= MUX_MMC7L;
+				when MUX_MMC7L   => mux_state <= MUX_D0RD_1;
+				when MUX_D0RD_1  => mux_state <= MUX_D1RD_1;
+				when MUX_D1RD_1  => mux_state <= MUX_MMC7H;
+				when MUX_MMC7H   => mux_state <= MUX_D0RD_2;
+				when MUX_D0RD_2  => mux_state <= MUX_D1RD_2;
+				when MUX_D1RD_2  => mux_state <= MUX_WAIT0;
+				end case;
+			end if;
+			if reset = '1' then
+				mux_c128_timeout <= (others => '1');
+-- 				system_wait <= '1';
+			end if;
+		end if;
+	end process;
+
+	-- MUX read
+	process(clk_mux)
+	begin
+		if rising_edge(clk_mux) then
+			if mux_clk_reg = '1' then
+				case mux_reg is
+				when X"0" =>
+					c64_data_reg(3 downto 0) <= mux_q;
+				when X"1" =>
+					c64_data_reg(7 downto 4) <= mux_q;
+				when X"6" =>
+					c64_reset_reg <= not mux_q(0);
+					c64_irq_n <= mux_q(2);
+					c64_nmi_n <= mux_q(3);
+					reset_pending <= reset or c64_reset_reg;
+					if reset_pending = '0' then
+						reset_in <= c64_reset_reg;
+					else
+						reset_in <= '0';
+					end if;
+					if no_clock_loc = '1' then
+						c64_irq_n <= '1';
+					end if;
+				when X"7" =>
+					c64_ba_reg <= mux_q(1);
+					if no_clock_loc = '1' then
+						c64_ba_reg <= '1';
+					end if;
+				when X"B" =>
+					button_reset_n <= mux_q(1);
+					ir <= mux_q(3);
+				when X"D" =>
+					iec_dat_reg <= mux_q(0);
+					iec_clk_reg <= mux_q(1);
+					iec_srq_reg <= mux_q(2);
+					iec_atn_reg <= mux_q(3);
+				when X"E" =>
+					ps2_keyboard_dat_in <= mux_q(0);
+					ps2_keyboard_clk_in <= mux_q(1);
+					ps2_mouse_dat_in <= mux_q(2);
+					ps2_mouse_clk_in <= mux_q(3);
+				when others =>
+					null;
+				end case;
+				if spi_sample = '1' then
+					spi_q_reg <= spi_q_reg(6 downto 0) & spi_miso;
+				end if;
+			end if;
+			iec_dat_in <= iec_dat_reg;
+			iec_clk_in <= iec_clk_reg;
+			iec_srq_in <= iec_srq_reg;
+			iec_atn_in <= iec_atn_reg;
+		end if;
+	end process;
+
+	-- MUX write
+	process(clk_mux)
+	begin
+		if rising_edge(clk_mux) then
+			spi_raw_ack <= '0';
+			if mux_clk_reg = '1' then
+				spi_sample <= '0';
+				case mux_state is
+--
+-- RESET
+				when MUX_RESET =>
+					mux_d_reg <= (others => '-');
+					mux_reg <= X"F";
+--
+-- MMC
+				when MUX_MMC0L =>
+					-- Remember current state for lowspeed transfer.
+					-- Register is accessed another 15 times in
+					-- system cycle, but should not be updated when running on 250khz speed.
+					mux_d_mmc(0) <= mmc_state(1) or (not mmc_state(5));
+					mux_d_mmc(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
+					-- Update register
+					mux_d_reg(0) <= mmc_state(1) or (not mmc_state(5));
+					mux_d_reg(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
+					mux_d_reg(2) <= mmc_cs_n; 
+					mux_d_reg(3) <= to_usb_rx;
+					mux_reg <= X"C";
+					if mmc_state(5) = '1' then
+						if spi_speed = '0' then
+							-- Slow speed. Only toggle once in two cycles
+							mmc_state <= mmc_state + "000001";
+							if mmc_state(1 downto 0) = "11" then
+								spi_sample <= '1';
+							end if;
+						else
+							-- Fast speed. Toggle 16 times in a cycle
+							mmc_state <= mmc_state + "000010";
+							if mmc_state(1) = '1' then
+								spi_sample <= '1';
+							end if;
+						end if;
+					end if;
+					if enable_raw_spi then
+						mux_d_reg(0) <= spi_raw_clk;
+						mux_d_reg(1) <= spi_raw_mosi;
+						mux_d_reg(2) <= mmc_cs_n; 
+						mux_d_reg(3) <= to_usb_rx;
+						mux_reg <= X"C";
+						spi_raw_ack <= '1';
+					end if;
+				when MUX_MMC1L | MUX_MMC2L | MUX_MMC3L
+				   | MUX_MMC4L | MUX_MMC5L | MUX_MMC6L | MUX_MMC7L =>
+					mux_d_reg(0) <= mux_d_mmc(0);
+					mux_d_reg(1) <= mux_d_mmc(1);
+					mux_d_reg(2) <= mmc_cs_n; 
+					mux_d_reg(3) <= to_usb_rx;
+					mux_reg <= X"C";
+					-- Only update register on when running at fast speed (8Mhz).
+					if (mmc_state(5) = '1') and (spi_speed = '1') then
+						mux_d_reg(0) <= mmc_state(1);
+						mux_d_reg(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
+						-- Fast speed. Toggle 16 times in a cycle
+						mmc_state <= mmc_state + "000010";
+						if mmc_state(1) = '1' then
+							spi_sample <= '1';
+						end if;
+					end if;
+					if enable_raw_spi then
+						mux_d_reg(0) <= spi_raw_clk;
+						mux_d_reg(1) <= spi_raw_mosi;
+						mux_d_reg(2) <= mmc_cs_n;
+						mux_d_reg(3) <= to_usb_rx;
+						mux_reg <= X"C";
+						spi_raw_ack <= '1';
+					end if;
+
+				when MUX_MMC0H | MUX_MMC1H | MUX_MMC2H | MUX_MMC3H
+				   | MUX_MMC4H | MUX_MMC5H | MUX_MMC6H | MUX_MMC7H =>
+					mux_d_reg(0) <= mux_d_mmc(0);
+					mux_d_reg(1) <= mux_d_mmc(1);
+					mux_d_reg(2) <= mmc_cs_n;
+					mux_d_reg(3) <= to_usb_rx;
+					mux_reg <= X"C";
+					if (mmc_state(5) = '1') and (spi_speed = '1') then
+						-- Only update register on when running at fast speed (8Mhz).
+						mux_d_reg(0) <= mmc_state(1);
+						mux_d_reg(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
+						-- Fast speed. Toggle 16 times in a cycle
+						mmc_state <= mmc_state + "000010";
+						if mmc_state(1) = '1' then
+							spi_sample <= '1';
+						end if;
+					elsif enable_iec_access then
+						-- When MMC transfer is not pending use some of the MMC cycles for IEC transfers.
+						mux_d_reg(0) <= iec_dat_out;
+						mux_d_reg(1) <= iec_clk_out;
+						mux_d_reg(2) <= iec_srq_out;
+						mux_d_reg(3) <= iec_atn_out;
+						mux_reg <= X"D";
+					end if;
+					if enable_raw_spi then
+						mux_d_reg(0) <= spi_raw_clk;
+						mux_d_reg(1) <= spi_raw_mosi;
+						mux_d_reg(2) <= mmc_cs_n;
+						mux_d_reg(3) <= to_usb_rx;
+						mux_reg <= X"C";
+						spi_raw_ack <= '1';
+					end if;
+				when MUX_NMIIRQ1 | MUX_NMIIRQ2=>
+					mux_d_reg <= "110" & (not reset);
+					mux_reg <= X"6";
+					if docking_station_loc = '1' then
+						mux_d_reg(2) <= docking_irq;
+					end if;
+--
+-- IEC
+				when MUX_IEC1 | MUX_IEC2 | MUX_IEC3 | MUX_IEC4 =>
+					mux_d_reg(0) <= iec_dat_out;
+					mux_d_reg(1) <= iec_clk_out;
+					mux_d_reg(2) <= iec_srq_out;
+					mux_d_reg(3) <= iec_atn_out;
+					mux_reg <= X"D";
+--
+-- USART, LEDs and IR
+				when MUX_LED =>
+					mux_d_reg <= flash_cs_n & rtc_cs & led_green & led_red;
+					mux_reg <= X"B";
+--
+-- PS2
+				when MUX_PS2 =>
+					mux_d_reg(0) <= ps2_keyboard_dat_out;
+					mux_d_reg(1) <= ps2_keyboard_clk_out;
+					mux_d_reg(2) <= ps2_mouse_dat_out;
+					mux_d_reg(3) <= ps2_mouse_clk_out;
+					mux_reg <= X"E";
+--
+-- WAITS
+				when MUX_WAIT0 =>
+					if spi_req /= spi_run then
+						spi_run <= spi_req;
+						mmc_state <= "100000";
+					end if;
+					-- Use dead time to do IEC reads/writes
+					mux_d_reg(0) <= iec_dat_out;
+					mux_d_reg(1) <= iec_clk_out;
+					mux_d_reg(2) <= iec_srq_out;
+					mux_d_reg(3) <= iec_atn_out;
+					mux_reg <= X"D";
+					if enable_raw_spi then
+						mux_d_reg(0) <= spi_raw_clk;
+						mux_d_reg(1) <= spi_raw_mosi;
+						mux_d_reg(2) <= mmc_cs_n;
+						mux_d_reg(3) <= to_usb_rx;
+						mux_reg <= X"C";
+						spi_raw_ack <= '1';
+					end if;
+				when MUX_WAIT1 =>
+					-- Continue BUSVIC output at end of phi2=0, so we sample BA a few times.
+					mux_d_reg <= "0101";
+					if docking_station_loc = '1' then
+						mux_d_reg <= "1111";
+					end if;
+					mux_reg <= X"7";
+					-- Toggle between SPI/IEC and updating BUSVIC.
+					if mux_toggle = '1' then
+						if enable_iec_access then
+							mux_d_reg(0) <= iec_dat_out;
+							mux_d_reg(1) <= iec_clk_out;
+							mux_d_reg(2) <= iec_srq_out;
+							mux_d_reg(3) <= iec_atn_out;
+							mux_reg <= X"D";
+						end if;
+						if enable_raw_spi then
+							mux_d_reg(0) <= spi_raw_clk;
+							mux_d_reg(1) <= spi_raw_mosi;
+							mux_d_reg(2) <= mmc_cs_n;
+							mux_d_reg(3) <= to_usb_rx;
+							mux_reg <= X"C";
+							spi_raw_ack <= '1';
+						end if;
+					end if;
+--
+-- PHI2  0
+				when MUX_A3_C =>
+					mux_d_reg <= X"C";
+					mux_reg <= X"5";
+				when MUX_BUSVIC =>
+					mux_d_reg <= "0101";
+					if docking_station_loc = '1' then
+						mux_d_reg <= "1111";
+					end if;
+					mux_reg <= X"7";
+				when MUX_ULTIMAX =>
+					mux_d_reg <= "1011";
+					mux_reg <= X"8";
+				when MUX_D0VIC =>
+					mux_d_reg <= c64_to_io(3 downto 0);
+					mux_reg <= X"0";
+				when MUX_D1VIC =>
+					mux_d_reg <= c64_to_io(7 downto 4);
+					mux_reg <= X"1";
+				when MUX_END0 =>
+					mux_d_reg <= "0111";
+					if docking_station_loc = '1' then
+						mux_d_reg <= "1111";
+					end if;
+					mux_reg <= X"7";
+--
+-- PHI2  1
+				when MUX_A0 =>
+					mux_d_reg <= c64_addr(3 downto 0);
+					mux_reg <= X"2";
+				when MUX_A1 =>
+					mux_d_reg <= c64_addr(7 downto 4);
+					mux_reg <= X"3";
+				when MUX_A2 =>
+					mux_d_reg <= c64_addr(11 downto 8);
+					mux_reg <= X"4";
+				when MUX_BUS =>
+					if c64_vic_loc = '0' then
+						if c64_cs_loc = '1' then
+							mux_d_reg <= "00" & (not c64_we_loc) & (not c64_we_loc);
+							mux_reg <= X"7";
+						end if;
+					else
+						-- A15..12 driven, A11..0 not driven, Data driven, no write.
+						mux_d_reg <= "0101";
+						mux_reg <= X"7";
+					end if;
+				when MUX_CLKPORT =>
+					-- GAME = low unless accessing roms
+					mux_d_reg <= "1" & c64_roms_loc & "11";
+					if c64_clockport_loc = '1' then
+						if c64_we_loc = '0' then
+							-- Clockport read
+							mux_d_reg <= "1010";
+						else
+							-- Clockport write
+							mux_d_reg <= "1001";
+						end if;
+					end if;
+					mux_reg <= X"8";
+				when MUX_A3 =>
+					if c64_vic_loc = '0' then
+						if c64_cs_loc = '1' then
+							mux_d_reg <= c64_addr(15 downto 12);
+							mux_reg <= X"5";
+						end if;
+					end if;
+--				when MUX_D0WR | MUX_D0WR_1 | MUX_D0WR_2 =>
+				when MUX_D0WR | MUX_D0WR_1 | MUX_D0WR_2 | MUX_D0RD_1 | MUX_D0RD_2 =>
+					mux_d_reg <= c64_to_io(3 downto 0);
+					mux_reg <= X"0";
+--				when MUX_D1WR | MUX_D1WR_1 | MUX_D1WR_2 =>
+				when MUX_D1WR | MUX_D1WR_1 | MUX_D1WR_2 | MUX_D1RD_1 | MUX_D1RD_2 =>
+					mux_d_reg <= c64_to_io(7 downto 4);
+					mux_reg <= X"1";
+				when others =>
+					null;
+				end case;
+			end if;
+		end if;
+	end process;
+
+	process(clk_mux)
+	begin
+		if rising_edge(clk_mux) then
+			if mmc_state(5) = '0' then
+				spi_ack <= spi_run;
+			end if;
+		end if;
+	end process;
+
+	mux_clk <= mux_clk_reg;
+	mux_d <= mux_d_reg;
+	mux <= mux_reg;
+end architecture;
diff --git a/sw/src/target/chameleon64/chameleon_io.vhd.bak b/sw/src/target/chameleon64/chameleon_io.vhd.bak
new file mode 100644
index 0000000..c534a13
--- /dev/null
+++ b/sw/src/target/chameleon64/chameleon_io.vhd.bak
@@ -0,0 +1,911 @@
+-- -----------------------------------------------------------------------
+--
+-- Turbo Chameleon
+--
+-- Multi purpose FPGA expansion for the Commodore 64 computer
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2013 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com
+--
+-- This source file is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published
+-- by the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This source file is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-- -----------------------------------------------------------------------
+--
+-- For better understanding what this entity does in detail, please refer
+-- to the Chameleon core-developers manual. It has documentation about
+-- the CPLD MUX, signal timing, docking-station protocol and the cartridge port access.
+--
+-- Chameleon timing and I/O driver. Handles all the timing and multiplexing
+-- details of the cartridge port and the CPLD mux.
+--   - Detects the type of mode the chameleon is running in.
+--   - Multiplexes the PS/2 keyboard and mouse signals.
+--   - Gives access to joysticks and keyboard on a C64 in cartridge mode.
+--   - Gives access to joysticks and keyboard on a docking-station
+--   - Gives access to MMC card and serial-flash through the CPLD MUX.
+--   - Drives the two LEDs on the Chameleon (or an optional Amiga keyboard).
+--   - Can optionally give access to the IEC bus
+--   - Can optionally give access to other C64 resources like the SID.
+--
+-- -----------------------------------------------------------------------
+-- enable_docking_station - Enable support for the docking-station.
+-- enable_c64_joykeyb     - Automatically read joystick and keyboard on the C64 bus.
+--                          Take note this disables the C64 bus access feature on this entity.
+-- enable_c64_4player     - Enable 4player support on the user-port of the C64.
+--                          The flag enable_c64_joykeyb must be true for this to work.
+-- enable_raw_spi         - SPI controller inside this entity is switched off.
+--                          And the actual SPI lines are exposed. The maximum speed is limited
+--                          as the signals are time multiplexed. The maximum spi speed usable
+--                          is around 1/12 of clk. (One line transition each 6 clk cycles)
+-- enable_iec_access      - Enables support for the IEC bus on the break-out cable.
+--                          Set this to 'false' when the IEC bus is not used to save some logic.
+-- -----------------------------------------------------------------------
+-- clk             - system clock
+-- ena_1mhz        - Enable must be '1' one clk cycle each 1 Mhz.
+-- reset           - Perform a reset of the subsystems
+-- reset_ext       - Hardware reset from the cartridge-port (eg. a C64 reset button)
+--
+-- no_clock        - '0' when connected to C64 cartridge port.
+--                   '1' when in standalone mode or docking-station connected.
+-- docking_station - '0' standalone/cartrdige mode
+--                   '1' when docking-station is connected.
+--
+-- to_usb_rx
+--
+-- The following timing signals are only useful when writing C64 related designs.
+-- They can be left unconnected in all other FPGA designs.
+-- phi_mode        - Selects timing in standalone mode ('0' is PAL, '1' is NTSC).
+-- phi_out         - Regenerated or synthesized phi2 clock.
+-- phi_cnt         - Counting the system-clock cycles within one phi2 cycle.
+-- phi_end_0       - The half of the cycle where phi_out is low ends.
+-- phi_end_1       - The half of the cycle where phi_out is high ends.
+-- phi_post_1      - Triggers when phi changes
+-- phi_post_2      - Triggers one cycle after phi changed
+-- phi_post_3      - Triggers two cycles phi changed
+-- phi_post_4      - Triggers three cycles phi changed
+--
+-- c64_irq_n       - Status of the C64 IRQ line (cartridge mode only)
+-- c64_nmi_n       - Status of the C64 NMI line
+-- c64_ba          - status of the C64 BA line
+--
+-- The following signals should be synchronised to the phi_out signal
+-- c64_vic         - When set data on c64_d is send to the VIC-II chip.
+-- c64_cs          - When set it accesses the C64 databus (uses Ultimax mode, no memory is mapped)
+-- c64_cs_roms     - Enables access to the C64 Kernal and Basic ROMs (disables Ultimax mode)
+-- c64_clockport   - When set it accesses the clockport.
+-- c64_we          - Access is a write when set (note polarity is the inverse of R/W on cartridge port)
+-- c64_a           - C64 address bus
+-- c64_d           - Data to the C64
+-- c64_q           - Data from the C64 (only valid when phi_end_1 is set)
+--
+-- spi_speed       - 0 SPI bus runs at slow speed (250 Kbit), SPI bus runs at fast speed (8 Mbit)
+-- spi_req         - Toggle to request SPI transfer.
+-- spi_ack         - Is made equal to spi_req after transfer is complete.
+-- spi_d           - Data input into SPI controller.
+-- spi_q           - Data output from SPI controller.
+--
+-- led_green       - Control the green LED (0 off, 1 on). Also power LED on Amiga keyboard.
+-- led_red         - Control the red LED (0 off, 1 on). Also drive LED on Amiga keyboard.
+-- ir              - ir signal. Input for the chameleon_cdtv_remote entity.
+--
+-- ps2_*           - PS2 signals for both keyboard and mouse.
+-- button_reset_n  - Status of blue reset button (right button) on the Chameleon. Low active.
+-- joystick*       - Joystick ports of both docking-station and C64.  Bits: fire2, fire1, right, left, down, up
+--                   The C64 only supports one button fire1. The signals are low active
+-- keys            - C64 keyboard. One bit for each key on the keyboard. Low active.
+-- restore_key_n   - Trigger for restore key on docking-station.
+--                   On a C64 the restore key is wired to the NMI line instead.
+-- iec_*           - IEC signals. Only valid when enable_iec_access is set to true.
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- -----------------------------------------------------------------------
+
+entity chameleon_io is
+	generic (
+		enable_docking_station : boolean := true;
+		enable_c64_joykeyb : boolean := false;
+		enable_c64_4player : boolean := false;
+		enable_raw_spi : boolean := false;
+		enable_iec_access : boolean := false
+	);
+	port (
+-- Clocks
+		clk : in std_logic;
+		clk_mux : in std_logic;
+		ena_1mhz : in std_logic;
+		reset : in std_logic;
+		reset_ext : out std_logic;
+
+-- Config
+		no_clock : out std_logic;
+		docking_station : out std_logic;
+
+-- Chameleon FPGA pins
+		-- C64 Clocks
+		phi2_n : in std_logic;
+		dotclock_n : in std_logic;
+		-- C64 cartridge control lines
+		io_ef_n : in std_logic;
+		rom_lh_n : in std_logic;
+		-- SPI bus
+		spi_miso : in std_logic;
+		-- CPLD multiplexer
+		mux_clk : out std_logic;
+		mux : out unsigned(3 downto 0);
+		mux_d : out unsigned(3 downto 0);
+		mux_q : in unsigned(3 downto 0);
+
+-- USB microcontroller (To RX of micro)
+		to_usb_rx : in std_logic := '1';
+
+-- C64 timing (only for C64 related cores)
+		phi_mode : in std_logic := '0';
+		phi_out : out std_logic;
+		phi_cnt : out unsigned(7 downto 0);
+		phi_end_0 : out std_logic;
+		phi_end_1 : out std_logic;
+		phi_post_1 : out std_logic;
+		phi_post_2 : out std_logic;
+		phi_post_3 : out std_logic;
+		phi_post_4 : out std_logic;
+
+-- C64 bus
+		c64_irq_n : out std_logic;
+		c64_nmi_n : out std_logic;
+		c64_ba : out std_logic;
+
+		c64_vic : in std_logic := '0';
+		c64_cs : in std_logic := '0';
+		c64_cs_roms : in std_logic := '0';
+		c64_clockport : in std_logic := '0';
+		c64_we : in std_logic := '0';
+		c64_a : in unsigned(15 downto 0) := (others => '0');
+		c64_d : in unsigned(7 downto 0) := (others => '1');
+		c64_q : out unsigned(7 downto 0);
+
+-- SPI chip-selects
+		mmc_cs_n : in std_logic := '1';
+		flash_cs_n : in std_logic := '1';
+		rtc_cs : in std_logic := '0';
+
+-- SPI controller (enable_raw_spi must be set to false)
+		spi_speed : in std_logic := '1';
+		spi_req : in std_logic := '0';
+		spi_ack : out std_logic;
+		spi_d : in unsigned(7 downto 0) := (others => '-');
+		spi_q : out unsigned(7 downto 0);
+
+-- SPI raw signals (enable_raw_spi must be set to true)
+		spi_raw_clk : in std_logic := '1';
+		spi_raw_mosi : in std_logic := '1';
+		
+-- LEDs
+		led_green : in std_logic := '0';
+		led_red : in std_logic := '0';
+		ir : out std_logic;
+
+-- PS/2 Keyboard
+		ps2_keyboard_clk_out: in std_logic := '1';
+		ps2_keyboard_dat_out: in std_logic := '1';
+		ps2_keyboard_clk_in: out std_logic;
+		ps2_keyboard_dat_in: out std_logic;
+
+-- PS/2 Mouse
+		ps2_mouse_clk_out: in std_logic := '1';
+		ps2_mouse_dat_out: in std_logic := '1';
+		ps2_mouse_clk_in: out std_logic;
+		ps2_mouse_dat_in: out std_logic;
+
+-- Buttons
+		button_reset_n : out std_logic;
+		
+-- Joysticks
+		joystick1 : out unsigned(5 downto 0);
+		joystick2 : out unsigned(5 downto 0);
+		joystick3 : out unsigned(5 downto 0);
+		joystick4 : out unsigned(5 downto 0);
+
+-- Keyboards
+		--  0 = col0, row0
+		--  1 = col1, row0
+		--  8 = col0, row1
+		-- 63 = col7, row7
+		keys : out unsigned(63 downto 0);
+		restore_key_n : out std_logic;
+		amiga_reset_n : out std_logic;
+		amiga_trigger : out std_logic;
+		amiga_scancode : out unsigned(7 downto 0);
+
+-- IEC bus
+		iec_clk_out : in std_logic := '1';
+		iec_dat_out : in std_logic := '1';
+		iec_atn_out : in std_logic := '1';
+		iec_srq_out : in std_logic := '1';
+		iec_clk_in : out std_logic;
+		iec_dat_in : out std_logic;
+		iec_atn_in : out std_logic;
+		iec_srq_in : out std_logic
+	);
+end entity;
+-- -----------------------------------------------------------------------
+
+architecture rtl of chameleon_io is
+-- Clocks
+	signal no_clock_loc : std_logic;
+	signal phi : std_logic;
+	signal end_of_phi_0 : std_logic;
+	signal end_of_phi_1 : std_logic;
+	
+-- State
+	signal reset_pending : std_logic := '0';
+	signal reset_in : std_logic := '0';
+
+-- MUX
+	type muxstate_t is (
+		-- Reset phase
+		MUX_RESET,
+		-- MMC
+		MUX_MMC0L, MUX_MMC0H, MUX_MMC1L, MUX_MMC1H, MUX_MMC2L, MUX_MMC2H, MUX_MMC3L, MUX_MMC3H,
+		MUX_MMC4L, MUX_MMC4H, MUX_MMC5L, MUX_MMC5H, MUX_MMC6L, MUX_MMC6H, MUX_MMC7L, MUX_MMC7H,
+		-- IEC
+		MUX_IEC1, MUX_IEC2, MUX_IEC3, MUX_IEC4,
+		-- PS2
+		MUX_PS2,
+		-- LED
+		MUX_LED,
+		-- PHI=0
+		MUX_WAIT0,
+		MUX_A3_C, MUX_BUSVIC,
+		MUX_D0VIC, MUX_D1VIC,
+		MUX_NMIIRQ1, MUX_NMIIRQ2,
+		MUX_ULTIMAX,
+		MUX_END0,
+		-- PHI=1
+		MUX_WAIT1,
+		MUX_BUS, MUX_CLKPORT,
+		MUX_A0, MUX_A1, MUX_A2, MUX_A3,
+		MUX_D0WR, MUX_D1WR, MUX_D0WR_1, MUX_D1WR_1, MUX_D0WR_2, MUX_D1WR_2,
+		MUX_D0RD_1, MUX_D1RD_1, MUX_D0RD_2, MUX_D1RD_2
+	);
+	signal mux_state : muxstate_t;
+	signal mux_toggle : std_logic := '0';
+
+	signal mux_c128_timeout : unsigned(7 downto 0) := (others => '1');
+	signal mux_clk_reg : std_logic := '0';
+	signal mux_d_reg : unsigned(mux_d'range) := X"F";
+	signal mux_reg : unsigned(mux'range) := X"F";
+	signal mux_d_mmc : unsigned(1 downto 0) := "11";
+
+-- C64 bus
+	signal c64_reset_reg : std_logic := '0';
+	signal c64_ba_reg : std_logic := '1';
+	signal c64_data_reg : unsigned(7 downto 0) := (others => '1');
+	signal c64_addr : unsigned(15 downto 0) := (others => '0');
+	signal c64_to_io : unsigned(7 downto 0) := (others => '0');
+	
+	signal c64_we_loc : std_logic := '0';
+	signal c64_vic_loc : std_logic := '0';
+	signal c64_cs_loc : std_logic := '0';
+	signal c64_roms_loc : std_logic := '0';
+	signal c64_clockport_loc : std_logic := '0';
+	
+-- C64 joystick/keyboard
+	signal c64_kb_req : std_logic := '0';
+	signal c64_kb_ack : std_logic := '0';
+	signal c64_kb_we : std_logic := '1';
+	signal c64_kb_a : unsigned(15 downto 0) := (others => '0');
+	signal c64_kb_q : unsigned(7 downto 0) := (others => '1');
+	signal c64_joystick1 : unsigned(4 downto 0);
+	signal c64_joystick2 : unsigned(4 downto 0);
+	signal c64_joystick3 : unsigned(4 downto 0);
+	signal c64_joystick4 : unsigned(4 downto 0);
+	signal c64_keys : unsigned(63 downto 0);
+
+-- Docking-station
+	signal docking_station_loc : std_logic;
+	signal docking_irq : std_logic;
+	signal docking_joystick1 : unsigned(5 downto 0);
+	signal docking_joystick2 : unsigned(5 downto 0);
+	signal docking_joystick3 : unsigned(5 downto 0);
+	signal docking_joystick4 : unsigned(5 downto 0);
+	signal docking_keys : unsigned(63 downto 0);
+	signal docking_amiga_reset_n : std_logic;
+	signal docking_amiga_scancode : unsigned(7 downto 0);
+
+-- MMC
+	signal mmc_state : unsigned(5 downto 0) := (others => '0');
+	signal spi_q_reg : unsigned(7 downto 0) := (others => '1');
+	signal spi_run : std_logic := '0';
+	signal spi_sample : std_logic := '0';
+	signal mmc_shift_req : std_logic;
+	signal mmc_shift_ack : std_logic := '0';
+
+-- IEC
+	signal iec_clk_reg : std_logic := '1';
+	signal iec_dat_reg : std_logic := '1';
+	signal iec_atn_reg : std_logic := '1';
+	signal iec_srq_reg : std_logic := '1';
+begin
+	reset_ext <= reset_in;
+	no_clock <= no_clock_loc;
+	docking_station <= docking_station_loc;
+	--
+	phi_out <= phi;
+	phi_end_0 <= end_of_phi_0;
+	phi_end_1 <= end_of_phi_1;
+	--
+	c64_ba <= c64_ba_reg;
+	c64_q <= c64_data_reg;
+	--
+	spi_q <= spi_q_reg;
+	--
+	joystick1 <= docking_joystick1 and ("1" & c64_joystick1);
+	joystick2 <= docking_joystick2 and ("1" & c64_joystick2);
+	joystick3 <= docking_joystick3 and ("1" & c64_joystick3);
+	joystick4 <= docking_joystick4 and ("1" & c64_joystick4);
+	keys <= docking_keys and c64_keys;
+
+-- -----------------------------------------------------------------------
+-- PHI2 clock sync
+-- -----------------------------------------------------------------------
+	phiInstance : entity work.chameleon_phi_clock
+		port map (
+			clk => clk,
+			phi2_n => phi2_n,
+			mode => phi_mode,
+
+			no_clock => no_clock_loc,
+			docking_station => docking_station_loc,
+
+			phiLocal => phi,
+			phiCnt => phi_cnt,
+			phiPreHalf => end_of_phi_0,
+			phiPreEnd => end_of_phi_1,
+			phiPost1 => phi_post_1,
+			phiPost2 => phi_post_2,
+			phiPost3 => phi_post_3,
+			phiPost4 => phi_post_4
+		);
+
+-- -----------------------------------------------------------------------
+-- Docking-station
+-- To enable set enable_docking_station to true.
+-- -----------------------------------------------------------------------
+	genDockingStation : if enable_docking_station generate
+		myDockingStation : entity work.chameleon_docking_station
+			port map (
+				clk => clk,
+				
+				docking_station => docking_station_loc,
+				
+				dotclock_n => dotclock_n,
+				io_ef_n => io_ef_n,
+				rom_lh_n => rom_lh_n,
+				irq_q => docking_irq,
+				
+				joystick1 => docking_joystick1,
+				joystick2 => docking_joystick2,
+				joystick3 => docking_joystick3,
+				joystick4 => docking_joystick4,
+				keys => docking_keys,
+				restore_key_n => restore_key_n,
+				
+				amiga_power_led => led_green,
+				amiga_drive_led => led_red,
+				amiga_reset_n => amiga_reset_n,
+				amiga_trigger => amiga_trigger,
+				amiga_scancode => amiga_scancode
+			);
+	end generate;
+
+	noDockingStation : if not enable_docking_station generate
+		docking_joystick1 <= (others => '1');
+		docking_joystick2 <= (others => '1');
+		docking_joystick3 <= (others => '1');
+		docking_joystick4 <= (others => '1');
+		docking_keys <= (others => '1');
+	end generate;
+
+-- -----------------------------------------------------------------------
+-- C64 keyboard and joystick support
+-- To enable set enable_c64_joykeyb to true.
+-- -----------------------------------------------------------------------
+	genC64JoyKeyb : if enable_c64_joykeyb generate
+		myC64JoyKeyb : entity work.chameleon_c64_joykeyb
+			generic map (
+				enable_4player => enable_c64_4player
+			)
+			port map (
+				clk => clk,
+				ena_1mhz => ena_1mhz,
+				no_clock => no_clock_loc,
+				reset => reset,
+				
+				ba => c64_ba_reg,
+				req => c64_kb_req,
+				ack => c64_kb_ack,
+				we => c64_kb_we,
+				a => c64_kb_a,
+				d => c64_data_reg,
+				q => c64_kb_q,
+				
+				joystick1 => c64_joystick1,
+				joystick2 => c64_joystick2,
+				joystick3 => c64_joystick3,
+				joystick4 => c64_joystick4,
+				keys => c64_keys
+			);
+
+		c64_addr <= c64_kb_a;
+		c64_to_io <= c64_kb_q;
+		c64_vic_loc <= '0';
+		c64_roms_loc <= '0';
+		c64_clockport_loc <= '0';
+		c64_we_loc <= c64_kb_we;
+
+		process(clk)
+		begin
+			if rising_edge(clk) then
+				if end_of_phi_1 = '1' then
+					c64_cs_loc <= '0';
+					if c64_kb_req /= c64_kb_ack then
+						if c64_cs_loc = '1' then
+							c64_kb_ack <= c64_kb_req;
+						else
+							c64_cs_loc <= '1';
+						end if;
+					end if;
+				end if;
+			end if;
+		end process;
+	end generate;
+	
+	noC64JoyKeyb : if not enable_c64_joykeyb generate
+		c64_joystick1 <= (others => '1');
+		c64_joystick2 <= (others => '1');
+		c64_joystick3 <= (others => '1');
+		c64_joystick4 <= (others => '1');
+		c64_keys <= (others => '1');
+		
+		c64_addr <= c64_a;
+		c64_to_io <= c64_d;
+
+		c64_vic_loc <= c64_vic;
+		c64_cs_loc <= c64_cs;
+		c64_roms_loc <= c64_cs_roms;
+		c64_clockport_loc <= c64_clockport;
+		c64_we_loc <= c64_we;
+	end generate;
+
+-- -----------------------------------------------------------------------
+-- MUX CPLD
+-- -----------------------------------------------------------------------
+	-- MUX clock
+	process(clk_mux)
+	begin
+		if rising_edge(clk_mux) then
+			mux_clk_reg <= not mux_clk_reg;
+		end if;
+	end process;
+
+	-- MUX sequence
+	process(clk_mux)
+	begin
+		if rising_edge(clk_mux) then
+			if mux_clk_reg = '1' then
+				mux_toggle <= not mux_toggle;
+				case mux_state is
+				when MUX_RESET   =>
+					if phi = '1' then
+						mux_state <= MUX_WAIT0;
+					end if;
+-- PHI2  0
+				when MUX_WAIT0   =>
+					if phi = '0' then
+						mux_state <= MUX_MMC0L;
+						if mux_c128_timeout /= 0 then
+							mux_c128_timeout <= mux_c128_timeout - 1;
+						end if;
+					end if;
+				when MUX_MMC0L   => mux_state <= MUX_A3_C;
+				when MUX_A3_C    => mux_state <= MUX_ULTIMAX;
+				when MUX_ULTIMAX => mux_state <= MUX_MMC0H;
+				when MUX_MMC0H   => mux_state <= MUX_BUSVIC;
+				when MUX_BUSVIC  => mux_state <= MUX_IEC1;
+				when MUX_IEC1    => mux_state <= MUX_MMC1L;
+				when MUX_MMC1L   => mux_state <= MUX_PS2;
+				when MUX_PS2     => mux_state <= MUX_A2;
+				when MUX_A2      => mux_state <= MUX_MMC1H;
+				when MUX_MMC1H   => mux_state <= MUX_NMIIRQ1;
+				when MUX_NMIIRQ1 => mux_state <= MUX_LED;
+				when MUX_LED     => mux_state <= MUX_MMC2L;
+				when MUX_MMC2L   => mux_state <= MUX_A0;
+				when MUX_A0      => mux_state <= MUX_IEC4;
+				when MUX_IEC4    => mux_state <= MUX_MMC2H;
+				when MUX_MMC2H   => mux_state <= MUX_A1;
+				when MUX_A1      => mux_state <= MUX_D0VIC;
+				when MUX_D0VIC   => mux_state <= MUX_D1VIC;
+				when MUX_D1VIC   => mux_state <= MUX_MMC3L;
+				when MUX_MMC3L   => mux_state <= MUX_IEC3;
+				when MUX_IEC3    => mux_state <= MUX_MMC3H;
+				when MUX_MMC3H   => mux_state <= MUX_END0;
+				when MUX_END0    => mux_state <= MUX_WAIT1;
+-- PHI2  1
+				when MUX_WAIT1 =>
+					if phi = '1' then
+						mux_state <= MUX_MMC4L;
+					end if;
+				when MUX_MMC4L   => mux_state <= MUX_BUS;
+				when MUX_BUS     => mux_state <= MUX_D0WR;
+				when MUX_D0WR    => mux_state <= MUX_D1WR;
+				when MUX_D1WR    => mux_state <= MUX_MMC4H;
+				when MUX_MMC4H   => mux_state <= MUX_A3;
+				when MUX_A3      => mux_state <= MUX_CLKPORT;
+				when MUX_CLKPORT => mux_state <= MUX_MMC5L;
+				when MUX_MMC5L   => mux_state <= MUX_NMIIRQ2;
+				when MUX_NMIIRQ2 => mux_state <= MUX_MMC5H;
+				when MUX_MMC5H   => mux_state <= MUX_D0WR_1;
+				when MUX_D0WR_1  => mux_state <= MUX_D1WR_1;
+				when MUX_D1WR_1  => mux_state <= MUX_MMC6L;
+				when MUX_MMC6L   => mux_state <= MUX_IEC2;
+				when MUX_IEC2    => mux_state <= MUX_MMC6H;
+				--when MUX_LED     => mux_state <= MUX_MMC6H;
+				when MUX_MMC6H   => mux_state <= MUX_D0WR_2;
+				when MUX_D0WR_2  => mux_state <= MUX_D1WR_2;
+				when MUX_D1WR_2  => mux_state <= MUX_MMC7L;
+				when MUX_MMC7L   => mux_state <= MUX_D0RD_1;
+				when MUX_D0RD_1  => mux_state <= MUX_D1RD_1;
+				when MUX_D1RD_1  => mux_state <= MUX_MMC7H;
+				when MUX_MMC7H   => mux_state <= MUX_D0RD_2;
+				when MUX_D0RD_2  => mux_state <= MUX_D1RD_2;
+				when MUX_D1RD_2  => mux_state <= MUX_WAIT0;
+				end case;
+			end if;
+			if reset = '1' then
+				mux_c128_timeout <= (others => '1');
+-- 				system_wait <= '1';
+			end if;
+		end if;
+	end process;
+
+	-- MUX read
+	process(clk_mux)
+	begin
+		if rising_edge(clk_mux) then
+			if mux_clk_reg = '1' then
+				case mux_reg is
+				when X"0" =>
+					c64_data_reg(3 downto 0) <= mux_q;
+				when X"1" =>
+					c64_data_reg(7 downto 4) <= mux_q;
+				when X"6" =>
+					c64_reset_reg <= not mux_q(0);
+					c64_irq_n <= mux_q(2);
+					c64_nmi_n <= mux_q(3);
+					reset_pending <= reset or c64_reset_reg;
+					if reset_pending = '0' then
+						reset_in <= c64_reset_reg;
+					else
+						reset_in <= '0';
+					end if;
+					if no_clock_loc = '1' then
+						c64_irq_n <= '1';
+					end if;
+				when X"7" =>
+					c64_ba_reg <= mux_q(1);
+					if no_clock_loc = '1' then
+						c64_ba_reg <= '1';
+					end if;
+				when X"B" =>
+					button_reset_n <= mux_q(1);
+					ir <= mux_q(3);
+				when X"D" =>
+					iec_dat_reg <= mux_q(0);
+					iec_clk_reg <= mux_q(1);
+					iec_srq_reg <= mux_q(2);
+					iec_atn_reg <= mux_q(3);
+				when X"E" =>
+					ps2_keyboard_dat_in <= mux_q(0);
+					ps2_keyboard_clk_in <= mux_q(1);
+					ps2_mouse_dat_in <= mux_q(2);
+					ps2_mouse_clk_in <= mux_q(3);
+				when others =>
+					null;
+				end case;
+				if spi_sample = '1' then
+					spi_q_reg <= spi_q_reg(6 downto 0) & spi_miso;
+				end if;
+			end if;
+			iec_dat_in <= iec_dat_reg;
+			iec_clk_in <= iec_clk_reg;
+			iec_srq_in <= iec_srq_reg;
+			iec_atn_in <= iec_atn_reg;
+		end if;
+	end process;
+
+	-- MUX write
+	process(clk_mux)
+	begin
+		if rising_edge(clk_mux) then
+			if mux_clk_reg = '1' then
+				spi_sample <= '0';
+				case mux_state is
+--
+-- RESET
+				when MUX_RESET =>
+					mux_d_reg <= (others => '-');
+					mux_reg <= X"F";
+--
+-- MMC
+				when MUX_MMC0L =>
+					-- Remember current state for lowspeed transfer.
+					-- Register is accessed another 15 times in
+					-- system cycle, but should not be updated when running on 250khz speed.
+					mux_d_mmc(0) <= mmc_state(1) or (not mmc_state(5));
+					mux_d_mmc(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
+					-- Update register
+					mux_d_reg(0) <= mmc_state(1) or (not mmc_state(5));
+					mux_d_reg(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
+					mux_d_reg(2) <= mmc_cs_n; 
+					mux_d_reg(3) <= to_usb_rx;
+					mux_reg <= X"C";
+					if mmc_state(5) = '1' then
+						if spi_speed = '0' then
+							-- Slow speed. Only toggle once in two cycles
+							mmc_state <= mmc_state + "000001";
+							if mmc_state(1 downto 0) = "11" then
+								spi_sample <= '1';
+							end if;
+						else
+							-- Fast speed. Toggle 16 times in a cycle
+							mmc_state <= mmc_state + "000010";
+							if mmc_state(1) = '1' then
+								spi_sample <= '1';
+							end if;
+						end if;
+					end if;
+					if enable_raw_spi then
+						mux_d_reg(0) <= spi_raw_clk;
+						mux_d_reg(1) <= spi_raw_mosi;
+						mux_d_reg(2) <= mmc_cs_n; 
+						mux_d_reg(3) <= to_usb_rx;
+						mux_reg <= X"C";
+					end if;
+				when MUX_MMC1L | MUX_MMC2L | MUX_MMC3L
+				   | MUX_MMC4L | MUX_MMC5L | MUX_MMC6L | MUX_MMC7L =>
+					mux_d_reg(0) <= mux_d_mmc(0);
+					mux_d_reg(1) <= mux_d_mmc(1);
+					mux_d_reg(2) <= mmc_cs_n; 
+					mux_d_reg(3) <= to_usb_rx;
+					mux_reg <= X"C";
+					-- Only update register on when running at fast speed (8Mhz).
+					if (mmc_state(5) = '1') and (spi_speed = '1') then
+						mux_d_reg(0) <= mmc_state(1);
+						mux_d_reg(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
+						-- Fast speed. Toggle 16 times in a cycle
+						mmc_state <= mmc_state + "000010";
+						if mmc_state(1) = '1' then
+							spi_sample <= '1';
+						end if;
+					end if;
+					if enable_raw_spi then
+						mux_d_reg(0) <= spi_raw_clk;
+						mux_d_reg(1) <= spi_raw_mosi;
+						mux_d_reg(2) <= mmc_cs_n;
+						mux_d_reg(3) <= to_usb_rx;
+						mux_reg <= X"C";
+					end if;
+
+				when MUX_MMC0H | MUX_MMC1H | MUX_MMC2H | MUX_MMC3H
+				   | MUX_MMC4H | MUX_MMC5H | MUX_MMC6H | MUX_MMC7H =>
+					mux_d_reg(0) <= mux_d_mmc(0);
+					mux_d_reg(1) <= mux_d_mmc(1);
+					mux_d_reg(2) <= mmc_cs_n;
+					mux_d_reg(3) <= to_usb_rx;
+					mux_reg <= X"C";
+					if (mmc_state(5) = '1') and (spi_speed = '1') then
+						-- Only update register on when running at fast speed (8Mhz).
+						mux_d_reg(0) <= mmc_state(1);
+						mux_d_reg(1) <= spi_d(7 - to_integer(mmc_state(4 downto 2)));
+						-- Fast speed. Toggle 16 times in a cycle
+						mmc_state <= mmc_state + "000010";
+						if mmc_state(1) = '1' then
+							spi_sample <= '1';
+						end if;
+					elsif enable_iec_access then
+						-- When MMC transfer is not pending use some of the MMC cycles for IEC transfers.
+						mux_d_reg(0) <= iec_dat_out;
+						mux_d_reg(1) <= iec_clk_out;
+						mux_d_reg(2) <= iec_srq_out;
+						mux_d_reg(3) <= iec_atn_out;
+						mux_reg <= X"D";
+					end if;
+					if enable_raw_spi then
+						mux_d_reg(0) <= spi_raw_clk;
+						mux_d_reg(1) <= spi_raw_mosi;
+						mux_d_reg(2) <= mmc_cs_n;
+						mux_d_reg(3) <= to_usb_rx;
+						mux_reg <= X"C";
+					end if;
+				when MUX_NMIIRQ1 | MUX_NMIIRQ2=>
+					mux_d_reg <= "110" & (not reset);
+					mux_reg <= X"6";
+					if docking_station_loc = '1' then
+						mux_d_reg(2) <= docking_irq;
+					end if;
+--
+-- IEC
+				when MUX_IEC1 | MUX_IEC2 | MUX_IEC3 | MUX_IEC4 =>
+					mux_d_reg(0) <= iec_dat_out;
+					mux_d_reg(1) <= iec_clk_out;
+					mux_d_reg(2) <= iec_srq_out;
+					mux_d_reg(3) <= iec_atn_out;
+					mux_reg <= X"D";
+--
+-- USART, LEDs and IR
+				when MUX_LED =>
+					mux_d_reg <= flash_cs_n & rtc_cs & led_green & led_red;
+					mux_reg <= X"B";
+--
+-- PS2
+				when MUX_PS2 =>
+					mux_d_reg(0) <= ps2_keyboard_dat_out;
+					mux_d_reg(1) <= ps2_keyboard_clk_out;
+					mux_d_reg(2) <= ps2_mouse_dat_out;
+					mux_d_reg(3) <= ps2_mouse_clk_out;
+					mux_reg <= X"E";
+--
+-- WAITS
+				when MUX_WAIT0 =>
+					if spi_req /= spi_run then
+						spi_run <= spi_req;
+						mmc_state <= "100000";
+					end if;
+					-- Use dead time to do IEC reads/writes
+					mux_d_reg(0) <= iec_dat_out;
+					mux_d_reg(1) <= iec_clk_out;
+					mux_d_reg(2) <= iec_srq_out;
+					mux_d_reg(3) <= iec_atn_out;
+					mux_reg <= X"D";
+					if enable_raw_spi then
+						mux_d_reg(0) <= spi_raw_clk;
+						mux_d_reg(1) <= spi_raw_mosi;
+						mux_d_reg(2) <= mmc_cs_n;
+						mux_d_reg(3) <= to_usb_rx;
+						mux_reg <= X"C";
+					end if;
+				when MUX_WAIT1 =>
+					-- Continue BUSVIC output at end of phi2=0, so we sample BA a few times.
+					mux_d_reg <= "0101";
+					if docking_station_loc = '1' then
+						mux_d_reg <= "1111";
+					end if;
+					mux_reg <= X"7";
+					-- Toggle between SPI/IEC and updating BUSVIC.
+					if mux_toggle = '1' then
+						if enable_iec_access then
+							mux_d_reg(0) <= iec_dat_out;
+							mux_d_reg(1) <= iec_clk_out;
+							mux_d_reg(2) <= iec_srq_out;
+							mux_d_reg(3) <= iec_atn_out;
+							mux_reg <= X"D";
+						end if;
+						if enable_raw_spi then
+							mux_d_reg(0) <= spi_raw_clk;
+							mux_d_reg(1) <= spi_raw_mosi;
+							mux_d_reg(2) <= mmc_cs_n;
+							mux_d_reg(3) <= to_usb_rx;
+							mux_reg <= X"C";
+						end if;
+					end if;
+--
+-- PHI2  0
+				when MUX_A3_C =>
+					mux_d_reg <= X"C";
+					mux_reg <= X"5";
+				when MUX_BUSVIC =>
+					mux_d_reg <= "0101";
+					if docking_station_loc = '1' then
+						mux_d_reg <= "1111";
+					end if;
+					mux_reg <= X"7";
+				when MUX_ULTIMAX =>
+					mux_d_reg <= "1011";
+					mux_reg <= X"8";
+				when MUX_D0VIC =>
+					mux_d_reg <= c64_to_io(3 downto 0);
+					mux_reg <= X"0";
+				when MUX_D1VIC =>
+					mux_d_reg <= c64_to_io(7 downto 4);
+					mux_reg <= X"1";
+				when MUX_END0 =>
+					mux_d_reg <= "0111";
+					if docking_station_loc = '1' then
+						mux_d_reg <= "1111";
+					end if;
+					mux_reg <= X"7";
+--
+-- PHI2  1
+				when MUX_A0 =>
+					mux_d_reg <= c64_addr(3 downto 0);
+					mux_reg <= X"2";
+				when MUX_A1 =>
+					mux_d_reg <= c64_addr(7 downto 4);
+					mux_reg <= X"3";
+				when MUX_A2 =>
+					mux_d_reg <= c64_addr(11 downto 8);
+					mux_reg <= X"4";
+				when MUX_BUS =>
+					if c64_vic_loc = '0' then
+						if c64_cs_loc = '1' then
+							mux_d_reg <= "00" & (not c64_we_loc) & (not c64_we_loc);
+							mux_reg <= X"7";
+						end if;
+					else
+						-- A15..12 driven, A11..0 not driven, Data driven, no write.
+						mux_d_reg <= "0101";
+						mux_reg <= X"7";
+					end if;
+				when MUX_CLKPORT =>
+					-- GAME = low unless accessing roms
+					mux_d_reg <= "1" & c64_roms_loc & "11";
+					if c64_clockport_loc = '1' then
+						if c64_we_loc = '0' then
+							-- Clockport read
+							mux_d_reg <= "1010";
+						else
+							-- Clockport write
+							mux_d_reg <= "1001";
+						end if;
+					end if;
+					mux_reg <= X"8";
+				when MUX_A3 =>
+					if c64_vic_loc = '0' then
+						if c64_cs_loc = '1' then
+							mux_d_reg <= c64_addr(15 downto 12);
+							mux_reg <= X"5";
+						end if;
+					end if;
+--				when MUX_D0WR | MUX_D0WR_1 | MUX_D0WR_2 =>
+				when MUX_D0WR | MUX_D0WR_1 | MUX_D0WR_2 | MUX_D0RD_1 | MUX_D0RD_2 =>
+					mux_d_reg <= c64_to_io(3 downto 0);
+					mux_reg <= X"0";
+--				when MUX_D1WR | MUX_D1WR_1 | MUX_D1WR_2 =>
+				when MUX_D1WR | MUX_D1WR_1 | MUX_D1WR_2 | MUX_D1RD_1 | MUX_D1RD_2 =>
+					mux_d_reg <= c64_to_io(7 downto 4);
+					mux_reg <= X"1";
+				when others =>
+					null;
+				end case;
+			end if;
+		end if;
+	end process;
+
+	process(clk_mux)
+	begin
+		if rising_edge(clk_mux) then
+			if mmc_state(5) = '0' then
+				spi_ack <= spi_run;
+			end if;
+		end if;
+	end process;
+
+	mux_clk <= mux_clk_reg;
+	mux_d <= mux_d_reg;
+	mux <= mux_reg;
+end architecture;
diff --git a/sw/src/target/chameleon64/chameleon_led.vhd b/sw/src/target/chameleon64/chameleon_led.vhd
new file mode 100644
index 0000000..e766ee0
--- /dev/null
+++ b/sw/src/target/chameleon64/chameleon_led.vhd
@@ -0,0 +1,67 @@
+-- -----------------------------------------------------------------------
+--
+-- Turbo Chameleon
+--
+-- Multi purpose FPGA expansion for the Commodore 64 computer
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- Your allowed to re-use this file for non-commercial applications
+-- developed for the Turbo Chameleon 64 cartridge. Either open or closed
+-- source whatever might be required by other licenses.
+--
+-- http://www.syntiac.com/chameleon.html
+-- -----------------------------------------------------------------------
+--
+-- LED blinker. Blink frequency 2 Hz
+--
+-- -----------------------------------------------------------------------
+-- clk       - system clock input
+-- clk_1khz  - 1 Khz clock input
+-- led_on    - if high the LED is on
+-- led_blink - if high the LED is blinking
+-- led       - led output (high is on) 2hz
+-- led_1hz   - led output 1 hz
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- -----------------------------------------------------------------------
+
+entity chameleon_led is
+	port (
+		clk : in std_logic;
+		clk_1khz : in std_logic;
+		
+		led_on : in std_logic;
+		led_blink : in std_logic;
+		led : out std_logic;
+		led_1hz : out std_logic
+	);
+end entity;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of chameleon_led is
+	signal count : unsigned(9 downto 0);
+begin
+	led <= count(8);
+	led_1hz <= count(9);
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if clk_1khz = '1' then
+				count <= count + 1;
+			end if;
+			if led_blink = '0' then
+				count(8) <= led_on;
+				count(9) <= led_on;
+			end if;					
+		end if;
+	end process;
+end architecture;
diff --git a/sw/src/target/chameleon64/chameleon_phi_clock_a.vhd b/sw/src/target/chameleon64/chameleon_phi_clock_a.vhd
new file mode 100644
index 0000000..87adbf9
--- /dev/null
+++ b/sw/src/target/chameleon64/chameleon_phi_clock_a.vhd
@@ -0,0 +1,163 @@
+-- -----------------------------------------------------------------------
+--
+-- VGA-64
+--
+-- Multi purpose FPGA expansion for the Commodore 64 computer
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2012 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/chameleon.html
+-- -----------------------------------------------------------------------
+--
+-- C64 Phi2-clock regeneration and divider
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of chameleon_phi_clock is
+--constant phaseShift : integer := 5; -- Number of cycles that FPGA runs ahead of measured phi.
+constant phaseShift : integer := 8; -- Number of cycles that FPGA runs ahead of measured phi.
+constant guardBits : integer := 4; -- Extra bits to reduce rounding errors in calculations
+signal phi2_n_reg : unsigned(7 downto 0);
+signal phiSync : std_logic := '0';
+
+signal locCnt : unsigned(7 downto 0) := (others => '0');
+signal fracCnt : unsigned(guardBits-1 downto 0) := (others => '0');
+signal c64Cnt : unsigned(7 downto 0) := (others => '0');
+signal slvCnt : unsigned(7 downto 0) := (others => '0');
+
+signal avgDelta : signed(8 downto 0) := (others => '0');
+signal avgLen : unsigned((7+guardBits) downto 0) := (others => '0');
+
+signal localPreHalf : std_logic := '0';
+signal localHalf : std_logic := '0';
+signal localPreEnd : std_logic := '0';
+signal localEnd : std_logic := '0';
+
+signal localPhi : std_logic := '0';
+
+signal localPost1 : std_logic := '0';
+signal localPost2 : std_logic := '0';
+signal localPost3 : std_logic := '0';
+signal localPost4 : std_logic := '0';
+begin
+	-- Average phi length
+	phiLength <= avgLen((7+guardBits) downto guardBits);
+	
+	-- Local generated phi
+	phiLocal <= localPhi;
+	
+	-- Cycle counter (add 1 to max-counter for each Mhz system clock)
+	-- For 100Mhz the cycle-counter runs to about 97 (NTSC) or 102 (PAL)
+	phiCnt <= locCnt;
+	phiPreHalf <= localPreHalf;
+	phiHalf <= localHalf;
+	phiPreEnd <= localPreEnd;
+	phiEnd <= localEnd;
+	
+	phiPost1 <= localPost1;
+	phiPost2 <= localPost2;
+	phiPost3 <= localPost3;
+	phiPost4 <= localPost4;
+
+	-- Input clock synchronizer
+	process(clk) is
+	begin
+		if rising_edge(clk) then
+			phiSync <= '0';
+			phi2_n_reg <= phi2_n_reg(phi2_n_reg'high-1 downto 0) & phi2_n;
+			-- Detect falling edge of phi2 (is rising edge here as phi2_n input is inverted).
+			if phi2_n_reg = "00000001" then
+				phiSync <= '1';
+			end if;
+		end if;
+	end process;
+
+	-- Determine cycle length
+	process(clk) is
+	begin
+		if rising_edge(clk) then
+			no_clock <= '0';
+			docking_station <= '0';
+			avgDelta <= (others => '0');
+			avgLen <= unsigned(signed(avgLen) + avgDelta);
+			
+			if (not c64Cnt) /= 0 then
+				c64Cnt <= c64Cnt + 1;
+			else
+				-- No Sync? Use internal speed.
+
+				-- Values for avgLen are determined experimentally using the testbench to measure actually speed.
+				-- Higher numbers slow down clock. Lower numbers speed clock up. Try a few times until optimum is reached
+				-- for particular system clock (100 Mhz at time of writing). Clocks can be accurate to atleast 3 digits with 4 guard bits.
+				-- PAL mode 0.985248 Mhz
+				avgLen <= to_unsigned(1703, 8+guardBits);
+				if mode = '1' then
+					-- NTSC mode 1.022727 Mhz
+					avgLen <= to_unsigned(1643, 8+guardBits);
+				end if;
+				if (phi2_n_reg(1) = '1') and (phi2_n_reg(2) = '1') and (phi2_n_reg(3) = '1') then
+					docking_station <= '1';
+				end if;
+				no_clock <= '1';
+			end if;
+			if phiSync = '1' then
+				avgDelta <= signed("0" & c64Cnt) - signed("0" & avgLen((7+guardBits) downto guardBits));
+				c64Cnt <= (others => '0');
+			end if;
+		end if;	
+	end process;
+
+	process(clk) is
+	begin
+		if rising_edge(clk) then
+			localPost1 <= localHalf or localEnd;
+			localPost2 <= localPost1;
+			localPost3 <= localPost2;
+			localPost4 <= localPost3;
+		end if;
+	end process;
+
+	process(clk) is
+		variable newFrac : unsigned(fracCnt'high+1 downto fracCnt'low);
+	begin
+		if rising_edge(clk) then
+			localPreHalf <= '0';
+			localHalf <= localPreHalf;
+			localPreEnd <= '0';
+			localEnd <= localPreEnd;
+			
+			locCnt <= locCnt + 1;
+			if slvCnt >=  avgLen((7+guardBits) downto guardBits) then
+				slvCnt <= (others => '0');
+			else
+				slvCnt <= slvCnt + 1;
+			end if;
+
+			if (slvCnt + phaseShift) = avgLen((7+guardBits) downto (1+guardBits)) then
+				localPreHalf <= '1';
+			end if;
+			if (slvCnt + phaseShift) = avgLen((7+guardBits) downto guardBits)
+			and localPhi = '1' then
+				localPreEnd <= '1';
+			end if;
+			if localHalf = '1' then
+				localPhi <= '1';
+			end if;
+			if localEnd = '1' then
+				-- Add fractional part to clock counter to have higher precision
+				newFrac := ("0" & fracCnt) + ("0" & (not avgLen(guardBits-1 downto 0)));
+				fracCnt <= newFrac(fracCnt'range);
+
+				localPhi <= '0';
+				locCnt <= (others => '0');
+				slvCnt <= c64Cnt + ("0000000" & newFrac(newFrac'high));
+			end if;
+		end if;
+	end process;
+end architecture;
diff --git a/sw/src/target/chameleon64/chameleon_phi_clock_e.vhd b/sw/src/target/chameleon64/chameleon_phi_clock_e.vhd
new file mode 100644
index 0000000..df53211
--- /dev/null
+++ b/sw/src/target/chameleon64/chameleon_phi_clock_e.vhd
@@ -0,0 +1,62 @@
+-- -----------------------------------------------------------------------
+--
+-- VGA-64
+--
+-- Multi purpose FPGA expansion for the Commodore 64 computer
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2012 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/chameleon.html
+-- -----------------------------------------------------------------------
+--
+-- C64 Phi2-clock regeneration and divider
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- -----------------------------------------------------------------------
+
+entity chameleon_phi_clock is
+	port (
+		clk : in std_logic;
+		phi2_n : in std_logic;
+		
+		-- Standalone mode, 0=PAL and 1=NTSC
+		mode : in std_logic := '0';
+		
+		-- Buffered and inverted phi_n (delayed)
+		phiLength : out unsigned(7 downto 0);
+		
+		-- no_clock is high when there are no phiIn changes detected.
+		-- This signal allows switching between real I/O and internal emulation.
+		no_clock : out std_logic;
+		
+		-- docking_station is high when there are no phiIn changes (no_clock) and
+		-- the phi signal is low. Without docking station phi is pulled up.
+		docking_station : out std_logic;
+
+		-- Resynthesised Phi2 clock
+		phiLocal : out std_logic;
+		-- Cycle counter
+		phiCnt : out unsigned(7 downto 0);
+		-- Control pulses
+		phiPreHalf : out std_logic;
+		phiHalf : out std_logic;
+		phiPreEnd : out std_logic;
+		phiEnd : out std_logic;
+
+		-- First cycle where phiLocal is changed.
+		phiPost1 : out std_logic;
+		-- Second cycle after phiLocal change.
+		phiPost2 : out std_logic;
+		-- Third cycle after phiLocal change.
+		phiPost3 : out std_logic;
+		-- Forth cycle after phiLocal change.
+		phiPost4 : out std_logic
+	);
+end entity;
+
+
diff --git a/sw/src/target/chameleon64/custom_io.vhd b/sw/src/target/chameleon64/custom_io.vhd
new file mode 100644
index 0000000..7fe8da5
--- /dev/null
+++ b/sw/src/target/chameleon64/custom_io.vhd
@@ -0,0 +1,25 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.target_pkg.all;
+use work.platform_pkg.all;
+use work.project_pkg.all;
+
+entity custom_io is
+  port
+  (
+    project_i         : out from_PROJECT_IO_t;
+    project_o         : in to_PROJECT_IO_t;
+    platform_i        : out from_PLATFORM_IO_t;
+    platform_o        : in to_PLATFORM_IO_t;
+    target_i          : out from_TARGET_IO_t;
+    target_o          : in to_TARGET_IO_t
+  );
+end entity custom_io;
+
+architecture SYN of custom_io is
+
+begin
+end architecture SYN;
diff --git a/sw/src/target/chameleon64/target_pkg.vhd b/sw/src/target/chameleon64/target_pkg.vhd
new file mode 100644
index 0000000..b597fe3
--- /dev/null
+++ b/sw/src/target/chameleon64/target_pkg.vhd
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.pace_pkg.all;
+
+package target_pkg is
+
+	--  
+	-- PACE constants which *MUST* be defined
+	--
+constant PACE_TARGET      : PACETargetType := PACE_TARGET_CHAMELEON64;
+constant PACE_FPGA_VENDOR : PACEFpgaVendor_t := PACE_FPGA_VENDOR_ALTERA;
+constant PACE_FPGA_FAMILY : PACEFpgaFamily_t := PACE_FPGA_FAMILY_CYCLONE3;
+
+constant PACE_CLKIN0      : natural := 50;
+constant PACE_HAS_SPI     : boolean := false;
+
+	--
+	-- DE1-specific constants
+	--
+  type from_TARGET_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+  type to_TARGET_IO_t is record
+    not_used  : std_logic;
+  end record;
+  
+ end;
diff --git a/sw/src/target/chameleon64/target_pkg.vhd.bak b/sw/src/target/chameleon64/target_pkg.vhd.bak
new file mode 100644
index 0000000..92749b8
--- /dev/null
+++ b/sw/src/target/chameleon64/target_pkg.vhd.bak
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.pace_pkg.all;
+
+package target_pkg is
+
+	--  
+	-- PACE constants which *MUST* be defined
+	--
+constant PACE_TARGET      : PACETargetType := PACE_TARGET_RETRORAMBLINGS_CYC3;
+constant PACE_FPGA_VENDOR : PACEFpgaVendor_t := PACE_FPGA_VENDOR_ALTERA;
+constant PACE_FPGA_FAMILY : PACEFpgaFamily_t := PACE_FPGA_FAMILY_CYCLONE3;
+
+constant PACE_CLKIN0      : natural := 50;
+constant PACE_HAS_SPI     : boolean := false;
+
+	--
+	-- DE1-specific constants
+	--
+  type from_TARGET_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+  type to_TARGET_IO_t is record
+    not_used  : std_logic;
+  end record;
+  
+ end;
diff --git a/sw/src/target/chameleon64/target_top.vhd b/sw/src/target/chameleon64/target_top.vhd
new file mode 100644
index 0000000..f6421cb
--- /dev/null
+++ b/sw/src/target/chameleon64/target_top.vhd
@@ -0,0 +1,424 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.sdram_pkg.all;
+use work.video_controller_pkg.all;
+use work.maple_pkg.all;
+use work.gamecube_pkg.all;
+use work.project_pkg.all;
+use work.platform_pkg.all;
+use work.target_pkg.all;
+
+
+entity target_top is
+  port
+    (
+-- Clocks
+		clk8 : in std_logic;
+		phi2_n : in std_logic;
+		dotclock_n : in std_logic;
+
+-- Bus
+		romlh_n : in std_logic;
+		ioef_n : in std_logic;
+
+-- Buttons
+		freeze_n : in std_logic;
+
+-- MMC/SPI
+		spi_miso : in std_logic;
+		mmc_cd_n : in std_logic;
+		mmc_wp : in std_logic;
+
+-- MUX CPLD
+		mux_clk : out std_logic;
+		mux : out unsigned(3 downto 0);
+		mux_d : out unsigned(3 downto 0);
+		mux_q : in unsigned(3 downto 0);
+
+-- USART
+		usart_tx : in std_logic;
+		usart_clk : in std_logic;
+		usart_rts : in std_logic;
+		usart_cts : in std_logic;
+
+-- SDRam
+		sd_clk : out std_logic;
+		sd_data : inout unsigned(15 downto 0);
+		sd_addr : out unsigned(12 downto 0);
+		sd_we_n : out std_logic;
+		sd_ras_n : out std_logic;
+		sd_cas_n : out std_logic;
+		sd_ba_0 : out std_logic;
+		sd_ba_1 : out std_logic;
+		sd_ldqm : out std_logic;
+		sd_udqm : out std_logic;
+
+-- Video
+		red : out std_logic_vector(4 downto 0);
+		grn : out std_logic_vector(4 downto 0);
+		blu : out std_logic_vector(4 downto 0);
+		nHSync : out std_logic;
+		nVSync : out std_logic;
+
+-- Audio
+		sigmaL : out std_logic;
+		sigmaR : out std_logic
+	);
+  
+end target_top;
+
+architecture SYN of target_top is
+
+
+  signal init       	: std_logic := '1';  
+  signal clock_27       : std_logic;
+  signal CLOCK_100	: std_logic;
+  
+  signal clkrst_i       : from_CLKRST_t;
+  signal buttons_i      : from_BUTTONS_t;
+  signal switches_i     : from_SWITCHES_t;
+  signal leds_o         : to_LEDS_t;
+  signal inputs_i       : from_INPUTS_t;
+  signal flash_i        : from_FLASH_t;
+  signal flash_o        : to_FLASH_t;
+  signal sram_i			: from_SRAM_t;
+  signal sram_o			: to_SRAM_t;	
+  signal sdram_i        : from_SDRAM_t;
+  signal sdram_o        : to_SDRAM_t;
+  signal video_i        : from_VIDEO_t;
+  signal video_o        : to_VIDEO_t;
+  signal audio_i        : from_AUDIO_t;
+  signal audio_o        : to_AUDIO_t;
+  signal ser_i          : from_SERIAL_t;
+  signal ser_o          : to_SERIAL_t;
+  signal project_i      : from_PROJECT_IO_t;
+  signal project_o      : to_PROJECT_IO_t;
+  signal platform_i     : from_PLATFORM_IO_t;
+  signal platform_o     : to_PLATFORM_IO_t;
+  signal target_i       : from_TARGET_IO_t;
+  signal target_o       : to_TARGET_IO_t;
+
+  signal switches       : std_logic_vector(1 downto 0);
+  signal buttons        : std_logic_vector(1 downto 0);
+
+-- Chameleon signals
+
+	signal ena_1mhz : std_logic;
+	signal ena_1khz : std_logic;
+	
+-- System state
+	signal no_clock : std_logic;
+	signal docking_station : std_logic;
+	signal reset : std_logic;
+	signal button_reset_n : std_logic;
+
+-- LEDs
+	signal led_green : std_logic := '0';
+	signal led_red : std_logic := '0';
+	signal ir : std_logic;
+
+	signal joystick1 : unsigned(5 downto 0);
+	signal joystick2 : unsigned(5 downto 0);
+	signal joystick3 : unsigned(5 downto 0);
+	signal joystick4 : unsigned(5 downto 0);
+
+-- C64 keyboard
+	signal keys : unsigned(63 downto 0);
+	signal restore_key_n : std_logic;
+	signal c64_nmi_n : std_logic; -- Replaces restore_key_n in C64 mode.
+
+-- PS/2 Keyboard
+	signal ps2_keyboard_clk_in : std_logic;
+	signal ps2_keyboard_dat_in : std_logic;
+	signal ps2_keyboard_clk_out : std_logic;
+	signal ps2_keyboard_dat_out : std_logic;
+
+-- PS/2 Mouse
+	signal ps2_mouse_clk_in: std_logic;
+	signal ps2_mouse_dat_in: std_logic;
+	signal ps2_mouse_clk_out: std_logic;
+	signal ps2_mouse_dat_out: std_logic;
+
+	
+--//********************
+
+
+begin
+
+	sd_clk<='0'; -- Freeze SDRAM since we can't access sd_cs
+
+	switches<="00";
+	buttons <= freeze_n & usart_cts;
+
+-- // Need Clock 50Mhz to Clock 27Mhz
+
+	my1Mhz : entity work.chameleon_1mhz
+		generic map (
+			clk_ticks_per_usec => 100
+		)
+		port map (
+			clk => CLOCK_100,
+			ena_1mhz => ena_1mhz,
+			ena_1mhz_2 => open
+		);
+
+	my1Khz : entity work.chameleon_1khz
+		port map (
+			clk => CLOCK_100,
+			ena_1mhz => ena_1mhz,
+			ena_1khz => ena_1khz
+		); 
+
+
+-- -----------------------------------------------------------------------
+--
+-- The I/O driving entity. The actual thing this example is about ;-)
+--
+-- -----------------------------------------------------------------------
+	myIO : entity work.chameleon_io
+		generic map (
+			enable_docking_station => true,
+			enable_c64_joykeyb => true,
+			enable_c64_4player => true
+		)
+		port map (
+		-- Clocks
+			clk => CLOCK_100,
+			clk_mux => CLOCK_100,
+			ena_1mhz => ena_1MHz,
+			reset => init, -- reset,
+			
+			no_clock => no_clock,
+			docking_station => docking_station,
+			
+		-- Chameleon FPGA pins
+			-- C64 Clocks
+			phi2_n => phi2_n,
+			dotclock_n => dotclock_n,
+			-- C64 cartridge control lines
+			io_ef_n => ioef_n,
+			rom_lh_n => romlh_n,
+			-- SPI bus
+			spi_miso => spi_miso,
+			-- CPLD multiplexer
+			mux_clk => mux_clk,
+			mux => mux,
+			mux_d => mux_d,
+			mux_q => mux_q,
+
+		-- LEDs
+			led_green => led_green,
+			led_red => led_red,
+			ir => ir,
+		
+		-- PS/2 Keyboard
+			ps2_keyboard_clk_out => ps2_keyboard_clk_out,
+			ps2_keyboard_dat_out => ps2_keyboard_dat_out,
+			ps2_keyboard_clk_in => ps2_keyboard_clk_in,
+			ps2_keyboard_dat_in => ps2_keyboard_dat_in,
+	
+		-- PS/2 Mouse
+			ps2_mouse_clk_out => ps2_mouse_clk_out,
+			ps2_mouse_dat_out => ps2_mouse_dat_out,
+			ps2_mouse_clk_in => ps2_mouse_clk_in,
+			ps2_mouse_dat_in => ps2_mouse_dat_in,
+
+		-- Buttons
+			button_reset_n => button_reset_n,
+			spi_raw_clk => '0',
+			spi_raw_mosi => '0',
+
+		-- Joysticks
+			joystick1 => joystick1,
+			joystick2 => joystick2,
+			joystick3 => joystick3,
+			joystick4 => joystick4,
+
+		-- Keyboards
+			keys => keys,
+			restore_key_n => restore_key_n,
+			c64_nmi_n => c64_nmi_n
+			
+		);
+
+
+  BLK_CLOCKING : block
+  begin
+    clkrst_i.clk_ref <= CLOCK_100;
+  
+    GEN_PLL : if PACE_HAS_PLL generate
+    
+      pll_50_inst : entity work.pllclk_ez --entity work.pllclk_ez  --entity work.pll
+        port map
+        (
+          inclk0  => clk8,
+          c0      => clkrst_i.clk(0),  --30Mhz
+          c1      => clkrst_i.clk(1),  --40Mhz
+			 c2		=> CLOCK_100,
+          c3      => clock_27,         --27.27Mhz
+          c4      => clkrst_i.clk(2)   --18.46Mhz
+        );
+
+    end generate GEN_PLL;
+    
+    GEN_NO_PLL : if not PACE_HAS_PLL generate
+   
+      -- feed input clocks into PACE core
+      clkrst_i.clk(0) <= CLOCK_100;
+      clkrst_i.clk(1) <= clock_27;
+        
+    end generate GEN_NO_PLL;
+      
+  end block BLK_CLOCKING;
+	
+  -- FPGA STARTUP
+	-- should extend power-on reset if registers init to '0'
+	process (CLOCK_100)
+		variable count : std_logic_vector (15 downto 0) := (others => '0');
+	begin
+		if rising_edge(CLOCK_100) then
+			if count = X"FFFF" then
+				init <= '0';
+			else
+				count := count + 1;
+				init <= '1';
+			end if;
+		end if;
+	end process;
+
+  clkrst_i.arst <= init;
+  clkrst_i.arst_n <= not clkrst_i.arst;
+
+  GEN_RESETS : for i in 0 to 3 generate
+
+    process (clkrst_i.clk(i), clkrst_i.arst)
+      variable rst_r : std_logic_vector(2 downto 0) := (others => '0');
+    begin
+      if clkrst_i.arst = '1' then
+        rst_r := (others => '1');
+      elsif rising_edge(clkrst_i.clk(i)) then
+        rst_r := rst_r(rst_r'left-1 downto 0) & '0';
+      end if;
+      clkrst_i.rst(i) <= rst_r(rst_r'left);
+    end process;
+
+  end generate GEN_RESETS;
+
+      -- inputs
+
+       switches_i(0) <= switches(0);
+       switches_i(1) <= switches(1);
+
+       GEN_NO_JAMMA : if PACE_JAMMA = PACE_JAMMA_NONE generate
+		inputs_i.jamma_n.coin(1) <= buttons(0);
+		inputs_i.jamma_n.p(1).start <= buttons(1);
+		inputs_i.jamma_n.p(1).up <= joystick1(0);
+		inputs_i.jamma_n.p(1).down <= joystick1(1);
+		inputs_i.jamma_n.p(1).left <= joystick1(2);
+		inputs_i.jamma_n.p(1).right <= joystick1(3);
+		inputs_i.jamma_n.p(1).button(1) <= joystick1(4);
+		inputs_i.jamma_n.p(1).button(2) <= joystick1(5);
+		inputs_i.jamma_n.p(1).button(3) <= '1';
+		inputs_i.jamma_n.p(1).button(4) <= '1';
+		inputs_i.jamma_n.p(1).button(5) <= '1';
+        end generate GEN_NO_JAMMA;
+  
+	-- not currently wired to any inputs
+	inputs_i.jamma_n.coin_cnt <= (others => '1');
+	inputs_i.jamma_n.coin(2) <= '1';
+	inputs_i.jamma_n.p(2).start <= '1';
+	inputs_i.jamma_n.p(2).up <= '1';
+	inputs_i.jamma_n.p(2).down <= '1';
+	inputs_i.jamma_n.p(2).left <= '1';
+	inputs_i.jamma_n.p(2).right <= '1';
+	inputs_i.jamma_n.p(2).button <= (others => '1');
+	inputs_i.jamma_n.service <= '1';
+	inputs_i.jamma_n.tilt <= '1';
+	inputs_i.jamma_n.test <= '1';
+		
+  BLK_VIDEO : block
+  begin
+
+    video_i.clk <= clkrst_i.clk(1);	-- by convention
+    video_i.clk_ena <= '1';
+    video_i.reset <= clkrst_i.rst(1);
+    
+    red <= video_o.rgb.r(video_o.rgb.r'left downto video_o.rgb.r'left-4);
+    grn <= video_o.rgb.g(video_o.rgb.g'left downto video_o.rgb.g'left-4);
+    blu <= video_o.rgb.b(video_o.rgb.b'left downto video_o.rgb.b'left-4);
+    nHSync <= video_o.hsync;
+    nVSync <= video_o.vsync;
+ 
+  end block BLK_VIDEO;
+
+  BLK_AUDIO : block
+  begin
+  
+    dacl : entity work.sigma_delta_dac
+      port map (
+        clk     => CLOCK_100,
+        din     => audio_o.ldata(15 downto 8),
+        dout    => sigmaL
+      );        
+
+    dacr : entity work.sigma_delta_dac
+      port map (
+        clk     => CLOCK_100,
+        din     => audio_o.rdata(15 downto 8),
+        dout    => sigmaR
+      );        
+
+  end block BLK_AUDIO;
+ 
+ pace_inst : entity work.pace                                            
+   port map
+   (
+     -- clocks and resets
+     clkrst_i					=> clkrst_i,
+
+     -- misc inputs and outputs
+     buttons_i         => buttons_i,
+     switches_i        => switches_i,
+     leds_o            => open,
+     
+     -- controller inputs
+     inputs_i          => inputs_i,
+
+     	-- external ROM/RAM
+     flash_i           => flash_i,
+     flash_o           => flash_o,
+     sram_i        		=> sram_i,
+     sram_o        		=> sram_o,
+     sdram_i           => sdram_i,
+     sdram_o           => sdram_o,
+  
+      -- VGA video
+      video_i           => video_i,
+      video_o           => video_o,
+      
+      -- sound
+      audio_i           => audio_i,
+      audio_o           => audio_o,
+
+      -- SPI (flash)
+      spi_i.din         => '0',
+      spi_o             => open,
+  
+      -- serial
+      ser_i             => ser_i,
+      ser_o             => ser_o,
+      
+      -- custom i/o
+      project_i         => project_i,
+      project_o         => project_o,
+      platform_i        => platform_i,
+      platform_o        => platform_o,
+      target_i          => target_i,
+      target_o          => target_o
+    );
+end SYN;
diff --git a/sw/src/target/chameleon64/target_top.vhd.bak b/sw/src/target/chameleon64/target_top.vhd.bak
new file mode 100644
index 0000000..14c573c
--- /dev/null
+++ b/sw/src/target/chameleon64/target_top.vhd.bak
@@ -0,0 +1,279 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.sdram_pkg.all;
+use work.video_controller_pkg.all;
+use work.maple_pkg.all;
+use work.gamecube_pkg.all;
+use work.project_pkg.all;
+use work.platform_pkg.all;
+use work.target_pkg.all;
+
+entity target_top is
+  port
+    (
+      --////////////////////	Clock Input	 	////////////////////	 
+      CLOCK_50      : in std_logic_vector(1 downto 0);                       --	50 MHz
+      --////////////////////////	SPI	////////////////////////
+      SPI_SCK : in std_logic;
+      SPI_DI : in std_logic;
+      SPI_DO : out std_logic;
+      CONF_DATA0 : in std_logic;
+      --////////////////////////	Speaker		////////////////////////
+      AUDIO_L           : out std_logic;
+      AUDIO_R           : out std_logic;
+      --////////////////////	VGA		////////////////////////////
+      VGA_VS        : out std_logic;                        --	VGA H_SYNC
+      VGA_HS        : out std_logic;                        --	VGA V_SYNC
+      VGA_R         : out std_logic_vector(5 downto 0);     --	VGA Red[3:0]
+      VGA_G         : out std_logic_vector(5 downto 0);     --	VGA Green[3:0]
+      VGA_B         : out std_logic_vector(5 downto 0);      --	VGA Blue[3:0]
+
+      SDRAM_nCS     : out std_logic
+
+      -- DATA0	    : in std_logic;                          --	DATA0
+  );    
+  
+end target_top;
+
+architecture SYN of target_top is
+
+  component user_io
+    port ( SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic;
+           SPI_MISO : out std_logic;
+           JOY0 :     out std_logic_vector(5 downto 0);
+           SWITCHES : out std_logic_vector(1 downto 0);
+           BUTTONS : out std_logic_vector(1 downto 0);
+           CORE_TYPE : in std_logic_vector(7 downto 0)
+           );
+   end component user_io;
+
+  signal init       	: std_logic := '1';  
+  signal clock_27       : std_logic;
+  
+  signal clkrst_i       : from_CLKRST_t;
+  signal buttons_i      : from_BUTTONS_t;
+  signal switches_i     : from_SWITCHES_t;
+  signal leds_o         : to_LEDS_t;
+  signal inputs_i       : from_INPUTS_t;
+  signal flash_i        : from_FLASH_t;
+  signal flash_o        : to_FLASH_t;
+  signal sram_i			: from_SRAM_t;
+  signal sram_o			: to_SRAM_t;	
+  signal sdram_i        : from_SDRAM_t;
+  signal sdram_o        : to_SDRAM_t;
+  signal video_i        : from_VIDEO_t;
+  signal video_o        : to_VIDEO_t;
+  signal audio_i        : from_AUDIO_t;
+  signal audio_o        : to_AUDIO_t;
+  signal ser_i          : from_SERIAL_t;
+  signal ser_o          : to_SERIAL_t;
+  signal project_i      : from_PROJECT_IO_t;
+  signal project_o      : to_PROJECT_IO_t;
+  signal platform_i     : from_PLATFORM_IO_t;
+  signal platform_o     : to_PLATFORM_IO_t;
+  signal target_i       : from_TARGET_IO_t;
+  signal target_o       : to_TARGET_IO_t;
+
+  signal joystick       : std_logic_vector(5 downto 0);
+  signal switches       : std_logic_vector(1 downto 0);
+  signal buttons        : std_logic_vector(1 downto 0);
+  
+--//********************
+
+begin
+
+  SDRAM_nCS <= '1';   -- don't select SDRAM
+
+-- // Need Clock 50Mhz to Clock 27Mhz
+
+  BLK_CLOCKING : block
+  begin
+    clkrst_i.clk_ref <= CLOCK_50(0);
+  
+    GEN_PLL : if PACE_HAS_PLL generate
+    
+      pll_50_inst : entity work.pllclk_ez --entity work.pllclk_ez  --entity work.pll
+        port map
+        (
+          inclk0  => CLOCK_50(0),
+          c0      => clkrst_i.clk(0),  --30Mhz
+          c1      => clkrst_i.clk(1),  --40Mhz
+          c3      => clock_27,         --27.27Mhz
+          c4      => clkrst_i.clk(2)   --18.46Mhz
+        );
+
+    end generate GEN_PLL;
+    
+    GEN_NO_PLL : if not PACE_HAS_PLL generate
+   
+      -- feed input clocks into PACE core
+      clkrst_i.clk(0) <= CLOCK_50(0);
+      clkrst_i.clk(1) <= clock_27;
+        
+    end generate GEN_NO_PLL;
+      
+  end block BLK_CLOCKING;
+	
+  -- FPGA STARTUP
+	-- should extend power-on reset if registers init to '0'
+	process (CLOCK_50(0))
+		variable count : std_logic_vector (11 downto 0) := (others => '0');
+	begin
+		if rising_edge(CLOCK_50(0)) then
+			if count = X"FFF" then
+				init <= '0';
+			else
+				count := count + 1;
+				init <= '1';
+			end if;
+		end if;
+	end process;
+
+  clkrst_i.arst <= init;
+  clkrst_i.arst_n <= not clkrst_i.arst;
+
+  GEN_RESETS : for i in 0 to 3 generate
+
+    process (clkrst_i.clk(i), clkrst_i.arst)
+      variable rst_r : std_logic_vector(2 downto 0) := (others => '0');
+    begin
+      if clkrst_i.arst = '1' then
+        rst_r := (others => '1');
+      elsif rising_edge(clkrst_i.clk(i)) then
+        rst_r := rst_r(rst_r'left-1 downto 0) & '0';
+      end if;
+      clkrst_i.rst(i) <= rst_r(rst_r'left);
+    end process;
+
+  end generate GEN_RESETS;
+
+      -- inputs
+      user_io_d : user_io
+        port map
+        (
+          SPI_CLK => SPI_SCK,
+          SPI_SS_IO => CONF_DATA0,
+          SPI_MISO => SPI_DO,
+          SPI_MOSI => SPI_DI,
+          JOY0 => joystick,
+          SWITCHES => switches,
+          BUTTONS => buttons,
+          CORE_TYPE => X"a2"            -- PACE core type
+          );
+
+       switches_i(0) <= switches(0);
+       switches_i(1) <= switches(1);
+
+       GEN_NO_JAMMA : if PACE_JAMMA = PACE_JAMMA_NONE generate
+		inputs_i.jamma_n.coin(1) <= not buttons(0);
+		inputs_i.jamma_n.p(1).start <= not buttons(1);
+		inputs_i.jamma_n.p(1).up <= not joystick(3);
+		inputs_i.jamma_n.p(1).down <= not joystick(2);
+		inputs_i.jamma_n.p(1).left <= not joystick(1);
+		inputs_i.jamma_n.p(1).right <= not joystick(0);
+		inputs_i.jamma_n.p(1).button(1) <= not joystick(4); 
+		inputs_i.jamma_n.p(1).button(2) <= not joystick(5); 
+		inputs_i.jamma_n.p(1).button(3) <= '1';
+		inputs_i.jamma_n.p(1).button(4) <= '1';
+		inputs_i.jamma_n.p(1).button(5) <= '1';
+        end generate GEN_NO_JAMMA;
+  
+	-- not currently wired to any inputs
+	inputs_i.jamma_n.coin_cnt <= (others => '1');
+	inputs_i.jamma_n.coin(2) <= '1';
+	inputs_i.jamma_n.p(2).start <= '1';
+	inputs_i.jamma_n.p(2).up <= '1';
+	inputs_i.jamma_n.p(2).down <= '1';
+	inputs_i.jamma_n.p(2).left <= '1';
+	inputs_i.jamma_n.p(2).right <= '1';
+	inputs_i.jamma_n.p(2).button <= (others => '1');
+	inputs_i.jamma_n.service <= '1';
+	inputs_i.jamma_n.tilt <= '1';
+	inputs_i.jamma_n.test <= '1';
+		
+  BLK_VIDEO : block
+  begin
+
+    video_i.clk <= clkrst_i.clk(1);	-- by convention
+    video_i.clk_ena <= '1';
+    video_i.reset <= clkrst_i.rst(1);
+    
+    VGA_R <= video_o.rgb.r(video_o.rgb.r'left downto video_o.rgb.r'left-5);
+    VGA_G <= video_o.rgb.g(video_o.rgb.g'left downto video_o.rgb.g'left-5);
+    VGA_B <= video_o.rgb.b(video_o.rgb.b'left downto video_o.rgb.b'left-5);
+    VGA_HS <= video_o.hsync;
+    VGA_VS <= video_o.vsync;
+ 
+  end block BLK_VIDEO;
+
+  BLK_AUDIO : block
+  begin
+  
+    dacl : entity work.sigma_delta_dac
+      port map (
+        clk     => CLOCK_50(0),
+        din     => audio_o.ldata(15 downto 8),
+        dout    => AUDIO_L
+      );        
+
+    dacr : entity work.sigma_delta_dac
+      port map (
+        clk     => CLOCK_50(0),
+        din     => audio_o.rdata(15 downto 8),
+        dout    => AUDIO_R
+      );        
+
+  end block BLK_AUDIO;
+ 
+ pace_inst : entity work.pace                                            
+   port map
+   (
+     -- clocks and resets
+     clkrst_i					=> clkrst_i,
+
+     -- misc inputs and outputs
+     buttons_i         => buttons_i,
+     switches_i        => switches_i,
+     leds_o            => open,
+     
+     -- controller inputs
+     inputs_i          => inputs_i,
+
+     	-- external ROM/RAM
+     flash_i           => flash_i,
+     flash_o           => flash_o,
+     sram_i        		=> sram_i,
+     sram_o        		=> sram_o,
+     sdram_i           => sdram_i,
+     sdram_o           => sdram_o,
+  
+      -- VGA video
+      video_i           => video_i,
+      video_o           => video_o,
+      
+      -- sound
+      audio_i           => audio_i,
+      audio_o           => audio_o,
+
+      -- SPI (flash)
+      spi_i.din         => '0',
+      spi_o             => open,
+  
+      -- serial
+      ser_i             => ser_i,
+      ser_o             => ser_o,
+      
+      -- custom i/o
+      project_i         => project_i,
+      project_o         => project_o,
+      platform_i        => platform_i,
+      platform_o        => platform_o,
+      target_i          => target_i,
+      target_o          => target_o
+    );
+end SYN;
diff --git a/sw/src/target/mist/custom_io.vhd b/sw/src/target/mist/custom_io.vhd
new file mode 100644
index 0000000..7fe8da5
--- /dev/null
+++ b/sw/src/target/mist/custom_io.vhd
@@ -0,0 +1,25 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.target_pkg.all;
+use work.platform_pkg.all;
+use work.project_pkg.all;
+
+entity custom_io is
+  port
+  (
+    project_i         : out from_PROJECT_IO_t;
+    project_o         : in to_PROJECT_IO_t;
+    platform_i        : out from_PLATFORM_IO_t;
+    platform_o        : in to_PLATFORM_IO_t;
+    target_i          : out from_TARGET_IO_t;
+    target_o          : in to_TARGET_IO_t
+  );
+end entity custom_io;
+
+architecture SYN of custom_io is
+
+begin
+end architecture SYN;
diff --git a/sw/src/target/mist/target_pkg.vhd b/sw/src/target/mist/target_pkg.vhd
new file mode 100644
index 0000000..0ff511e
--- /dev/null
+++ b/sw/src/target/mist/target_pkg.vhd
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.pace_pkg.all;
+
+package target_pkg is
+
+	--  
+	-- PACE constants which *MUST* be defined
+	--
+constant PACE_TARGET      : PACETargetType := PACE_TARGET_MIST;
+constant PACE_FPGA_VENDOR : PACEFpgaVendor_t := PACE_FPGA_VENDOR_ALTERA;
+constant PACE_FPGA_FAMILY : PACEFpgaFamily_t := PACE_FPGA_FAMILY_CYCLONE3;
+
+constant PACE_CLKIN0      : natural := 27;
+constant PACE_HAS_SPI     : boolean := false;
+
+	--
+	-- DE1-specific constants
+	--
+  type from_TARGET_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+  type to_TARGET_IO_t is record
+    not_used  : std_logic;
+  end record;
+  
+ end;
diff --git a/sw/src/target/mist/target_top.vhd b/sw/src/target/mist/target_top.vhd
new file mode 100644
index 0000000..6794a9d
--- /dev/null
+++ b/sw/src/target/mist/target_top.vhd
@@ -0,0 +1,271 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.sdram_pkg.all;
+use work.video_controller_pkg.all;
+use work.maple_pkg.all;
+use work.gamecube_pkg.all;
+use work.project_pkg.all;
+use work.platform_pkg.all;
+use work.target_pkg.all;
+
+entity target_top is
+  port
+    (
+      --////////////////////	Clock Input	 	////////////////////	 
+      CLOCK_27      : in std_logic_vector(1 downto 0);                       --	50 MHz
+      --////////////////////////	SPI	////////////////////////
+      SPI_SCK : in std_logic;
+      SPI_DI : in std_logic;
+      SPI_DO : out std_logic;
+      CONF_DATA0 : in std_logic;
+      --////////////////////////	Speaker		////////////////////////
+      AUDIO_L           : out std_logic;
+      AUDIO_R           : out std_logic;
+      --////////////////////	VGA		////////////////////////////
+      VGA_VS        : out std_logic;                        --	VGA H_SYNC
+      VGA_HS        : out std_logic;                        --	VGA V_SYNC
+      VGA_R         : out std_logic_vector(5 downto 0);     --	VGA Red[3:0]
+      VGA_G         : out std_logic_vector(5 downto 0);     --	VGA Green[3:0]
+      VGA_B         : out std_logic_vector(5 downto 0);      --	VGA Blue[3:0]
+
+      SDRAM_nCS     : out std_logic
+
+      -- DATA0	    : in std_logic;                          --	DATA0
+  );    
+  
+end target_top;
+
+architecture SYN of target_top is
+
+  component user_io
+    port ( SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic;
+           SPI_MISO : out std_logic;
+           JOY0 :     out std_logic_vector(5 downto 0);
+           SWITCHES : out std_logic_vector(1 downto 0);
+           BUTTONS : out std_logic_vector(1 downto 0);
+           CORE_TYPE : in std_logic_vector(7 downto 0)
+           );
+   end component user_io;
+
+  signal init       	: std_logic := '1';  
+  signal clock_50       : std_logic;
+  
+  signal clkrst_i       : from_CLKRST_t;
+  signal buttons_i      : from_BUTTONS_t;
+  signal switches_i     : from_SWITCHES_t;
+  signal leds_o         : to_LEDS_t;
+  signal inputs_i       : from_INPUTS_t;
+  signal flash_i        : from_FLASH_t;
+  signal flash_o        : to_FLASH_t;
+  signal sram_i			: from_SRAM_t;
+  signal sram_o			: to_SRAM_t;	
+  signal sdram_i        : from_SDRAM_t;
+  signal sdram_o        : to_SDRAM_t;
+  signal video_i        : from_VIDEO_t;
+  signal video_o        : to_VIDEO_t;
+  signal audio_i        : from_AUDIO_t;
+  signal audio_o        : to_AUDIO_t;
+  signal ser_i          : from_SERIAL_t;
+  signal ser_o          : to_SERIAL_t;
+  signal project_i      : from_PROJECT_IO_t;
+  signal project_o      : to_PROJECT_IO_t;
+  signal platform_i     : from_PLATFORM_IO_t;
+  signal platform_o     : to_PLATFORM_IO_t;
+  signal target_i       : from_TARGET_IO_t;
+  signal target_o       : to_TARGET_IO_t;
+
+  signal joystick       : std_logic_vector(5 downto 0);
+  signal switches       : std_logic_vector(1 downto 0);
+  signal buttons        : std_logic_vector(1 downto 0);
+  
+--//********************
+
+begin
+
+  SDRAM_nCS <= '1';   -- don't select SDRAM
+
+-- // Need Clock 50Mhz to Clock 27Mhz
+
+  BLK_CLOCKING : block
+  begin
+    clkrst_i.clk_ref <= CLOCK_27(0);
+  
+    GEN_PLL : if PACE_HAS_PLL generate
+    
+      pll_27_inst : entity work.pllclk_ez --entity work.pllclk_ez  --entity work.pll
+        port map
+        (
+          inclk0  => CLOCK_27(0),
+          c0      => clkrst_i.clk(0),  --30Mhz
+          c1      => clkrst_i.clk(1),  --40Mhz
+          c3      => clock_50,  --40Mhz
+          c4      => clkrst_i.clk(2)   --18.46Mhz
+        );
+
+    end generate GEN_PLL;
+    
+  end block BLK_CLOCKING;
+	
+  -- FPGA STARTUP
+	-- should extend power-on reset if registers init to '0'
+	process (clock_50)
+		variable count : std_logic_vector (11 downto 0) := (others => '0');
+	begin
+		if rising_edge(clock_50) then
+			if count = X"FFF" then
+				init <= '0';
+			else
+				count := count + 1;
+				init <= '1';
+			end if;
+		end if;
+	end process;
+
+  clkrst_i.arst <= init;
+  clkrst_i.arst_n <= not clkrst_i.arst;
+
+  GEN_RESETS : for i in 0 to 3 generate
+
+    process (clkrst_i.clk(i), clkrst_i.arst)
+      variable rst_r : std_logic_vector(2 downto 0) := (others => '0');
+    begin
+      if clkrst_i.arst = '1' then
+        rst_r := (others => '1');
+      elsif rising_edge(clkrst_i.clk(i)) then
+        rst_r := rst_r(rst_r'left-1 downto 0) & '0';
+      end if;
+      clkrst_i.rst(i) <= rst_r(rst_r'left);
+    end process;
+
+  end generate GEN_RESETS;
+
+      -- inputs
+      user_io_d : user_io
+        port map
+        (
+          SPI_CLK => SPI_SCK,
+          SPI_SS_IO => CONF_DATA0,
+          SPI_MISO => SPI_DO,
+          SPI_MOSI => SPI_DI,
+          JOY0 => joystick,
+          SWITCHES => switches,
+          BUTTONS => buttons,
+          CORE_TYPE => X"a2"            -- PACE core type
+          );
+
+       switches_i(0) <= switches(0);
+       switches_i(1) <= switches(1);
+
+       GEN_NO_JAMMA : if PACE_JAMMA = PACE_JAMMA_NONE generate
+		inputs_i.jamma_n.coin(1) <= not buttons(0);
+		inputs_i.jamma_n.p(1).start <= not buttons(1);
+		inputs_i.jamma_n.p(1).up <= not joystick(3);
+		inputs_i.jamma_n.p(1).down <= not joystick(2);
+		inputs_i.jamma_n.p(1).left <= not joystick(1);
+		inputs_i.jamma_n.p(1).right <= not joystick(0);
+		inputs_i.jamma_n.p(1).button(1) <= not joystick(4); 
+		inputs_i.jamma_n.p(1).button(2) <= not joystick(5); 
+		inputs_i.jamma_n.p(1).button(3) <= '1';
+		inputs_i.jamma_n.p(1).button(4) <= '1';
+		inputs_i.jamma_n.p(1).button(5) <= '1';
+        end generate GEN_NO_JAMMA;
+  
+	-- not currently wired to any inputs
+	inputs_i.jamma_n.coin_cnt <= (others => '1');
+	inputs_i.jamma_n.coin(2) <= '1';
+	inputs_i.jamma_n.p(2).start <= '1';
+	inputs_i.jamma_n.p(2).up <= '1';
+	inputs_i.jamma_n.p(2).down <= '1';
+	inputs_i.jamma_n.p(2).left <= '1';
+	inputs_i.jamma_n.p(2).right <= '1';
+	inputs_i.jamma_n.p(2).button <= (others => '1');
+	inputs_i.jamma_n.service <= '1';
+	inputs_i.jamma_n.tilt <= '1';
+	inputs_i.jamma_n.test <= '1';
+		
+  BLK_VIDEO : block
+  begin
+
+    video_i.clk <= clkrst_i.clk(1);	-- by convention
+    video_i.clk_ena <= '1';
+    video_i.reset <= clkrst_i.rst(1);
+    
+    VGA_R <= video_o.rgb.r(video_o.rgb.r'left downto video_o.rgb.r'left-5);
+    VGA_G <= video_o.rgb.g(video_o.rgb.g'left downto video_o.rgb.g'left-5);
+    VGA_B <= video_o.rgb.b(video_o.rgb.b'left downto video_o.rgb.b'left-5);
+    VGA_HS <= video_o.hsync;
+    VGA_VS <= video_o.vsync;
+ 
+  end block BLK_VIDEO;
+
+  BLK_AUDIO : block
+  begin
+  
+    dacl : entity work.sigma_delta_dac
+      port map (
+        clk     => CLOCK_27(0),
+        din     => audio_o.ldata(15 downto 8),
+        dout    => AUDIO_L
+      );        
+
+    dacr : entity work.sigma_delta_dac
+      port map (
+        clk     => CLOCK_27(0),
+        din     => audio_o.rdata(15 downto 8),
+        dout    => AUDIO_R
+      );        
+
+  end block BLK_AUDIO;
+ 
+ pace_inst : entity work.pace                                            
+   port map
+   (
+     -- clocks and resets
+     clkrst_i					=> clkrst_i,
+
+     -- misc inputs and outputs
+     buttons_i         => buttons_i,
+     switches_i        => switches_i,
+     leds_o            => open,
+     
+     -- controller inputs
+     inputs_i          => inputs_i,
+
+     	-- external ROM/RAM
+     flash_i           => flash_i,
+     flash_o           => flash_o,
+     sram_i        		=> sram_i,
+     sram_o        		=> sram_o,
+     sdram_i           => sdram_i,
+     sdram_o           => sdram_o,
+  
+      -- VGA video
+      video_i           => video_i,
+      video_o           => video_o,
+      
+      -- sound
+      audio_i           => audio_i,
+      audio_o           => audio_o,
+
+      -- SPI (flash)
+      spi_i.din         => '0',
+      spi_o             => open,
+  
+      -- serial
+      ser_i             => ser_i,
+      ser_o             => ser_o,
+      
+      -- custom i/o
+      project_i         => project_i,
+      project_o         => project_o,
+      platform_i        => platform_i,
+      platform_o        => platform_o,
+      target_i          => target_i,
+      target_o          => target_o
+    );
+end SYN;
diff --git a/sw/src/target/mist/user_io.v b/sw/src/target/mist/user_io.v
new file mode 100644
index 0000000..f0672c0
--- /dev/null
+++ b/sw/src/target/mist/user_io.v
@@ -0,0 +1,72 @@
+module user_io(
+	   input      SPI_CLK,
+	   input      SPI_SS_IO,
+	   output     reg SPI_MISO,
+	   input      SPI_MOSI,
+	   input [7:0] CORE_TYPE,
+		output [5:0] JOY0,
+		output [5:0] JOY1,
+		output [1:0] BUTTONS,
+		output [1:0] SWITCHES
+	   );
+
+   reg [6:0]         sbuf;
+   reg [7:0]         cmd;
+   reg [4:0] 	      cnt;
+   reg [5:0]         joystick0;
+   reg [5:0]         joystick1;
+   reg [3:0] 	      but_sw;
+
+	assign JOY0 = joystick0;
+	assign JOY1 = joystick1;
+	assign BUTTONS = but_sw[1:0];
+	assign SWITCHES = but_sw[3:2];
+   
+   always@(negedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+		   SPI_MISO <= 1'bZ;
+		end else begin
+	      if(cnt < 8) begin
+			  SPI_MISO <= CORE_TYPE[7-cnt];
+			end else begin
+		     SPI_MISO <= 1'bZ;
+			end
+	   end
+	end
+		
+   always@(posedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+        cnt <= 0;
+		end else begin
+			sbuf[6:1] <= sbuf[5:0];
+			sbuf[0] <= SPI_MOSI;
+
+			cnt <= cnt + 1;
+
+	      if(cnt == 7) begin
+			   cmd[7:1] <= sbuf; 
+				cmd[0] <= SPI_MOSI;
+		   end	
+
+	      if(cnt == 15) begin
+			   if(cmd == 1) begin
+					 but_sw[3:1] <= sbuf[2:0]; 
+					 but_sw[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 2) begin
+					 joystick0[5:1] <= sbuf[4:0]; 
+					 joystick0[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 3) begin
+					 joystick1[5:1] <= sbuf[4:0]; 
+					 joystick1[0] <= SPI_MOSI; 
+				end
+			end	
+		end
+	end
+   
+//   always@(posedge clk2) begin
+//      LED <= ~LED;
+//   end
+   
+endmodule
diff --git a/sw/src/target/retroramblings_c3/custom_io.vhd b/sw/src/target/retroramblings_c3/custom_io.vhd
new file mode 100644
index 0000000..7fe8da5
--- /dev/null
+++ b/sw/src/target/retroramblings_c3/custom_io.vhd
@@ -0,0 +1,25 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.target_pkg.all;
+use work.platform_pkg.all;
+use work.project_pkg.all;
+
+entity custom_io is
+  port
+  (
+    project_i         : out from_PROJECT_IO_t;
+    project_o         : in to_PROJECT_IO_t;
+    platform_i        : out from_PLATFORM_IO_t;
+    platform_o        : in to_PLATFORM_IO_t;
+    target_i          : out from_TARGET_IO_t;
+    target_o          : in to_TARGET_IO_t
+  );
+end entity custom_io;
+
+architecture SYN of custom_io is
+
+begin
+end architecture SYN;
diff --git a/sw/src/target/retroramblings_c3/target_pkg.vhd b/sw/src/target/retroramblings_c3/target_pkg.vhd
new file mode 100644
index 0000000..92749b8
--- /dev/null
+++ b/sw/src/target/retroramblings_c3/target_pkg.vhd
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.pace_pkg.all;
+
+package target_pkg is
+
+	--  
+	-- PACE constants which *MUST* be defined
+	--
+constant PACE_TARGET      : PACETargetType := PACE_TARGET_RETRORAMBLINGS_CYC3;
+constant PACE_FPGA_VENDOR : PACEFpgaVendor_t := PACE_FPGA_VENDOR_ALTERA;
+constant PACE_FPGA_FAMILY : PACEFpgaFamily_t := PACE_FPGA_FAMILY_CYCLONE3;
+
+constant PACE_CLKIN0      : natural := 50;
+constant PACE_HAS_SPI     : boolean := false;
+
+	--
+	-- DE1-specific constants
+	--
+  type from_TARGET_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+  type to_TARGET_IO_t is record
+    not_used  : std_logic;
+  end record;
+  
+ end;
diff --git a/sw/src/target/retroramblings_c3/target_top.vhd b/sw/src/target/retroramblings_c3/target_top.vhd
new file mode 100644
index 0000000..a186954
--- /dev/null
+++ b/sw/src/target/retroramblings_c3/target_top.vhd
@@ -0,0 +1,437 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.sdram_pkg.all;
+use work.video_controller_pkg.all;
+use work.maple_pkg.all;
+use work.gamecube_pkg.all;
+use work.project_pkg.all;
+use work.platform_pkg.all;
+use work.target_pkg.all;
+
+
+--entity C3BoardToplevel is
+--port(
+--		clk_50 	: in 	std_logic;
+--		reset_button : in std_logic;
+--		led_out : out 	std_logic;
+--
+--		-- SDRAM - chip 1
+--		sd1_addr : out std_logic_vector(11 downto 0);
+--		sd1_data : inout std_logic_vector(7 downto 0);
+--		sd1_ba : out std_logic_vector(1 downto 0);
+--		sdram1_clk : out std_logic;
+--		sd1_cke : out std_logic;
+--		sd1_dqm : out std_logic;
+--		sd1_cs : out std_logic;
+--		sd1_we : out std_logic;
+--		sd1_cas : out std_logic;
+--		sd1_ras : out std_logic;
+--
+--		-- SDRAM - chip 2
+--		sd2_addr : out std_logic_vector(11 downto 0);
+--		sd2_data : inout std_logic_vector(7 downto 0);
+--		sd2_ba : out std_logic_vector(1 downto 0);
+--		sdram2_clk : out std_logic;
+--		sd2_cke : out std_logic;
+--		sd2_dqm : out std_logic;
+--		sd2_cs : out std_logic;
+--		sd2_we : out std_logic;
+--		sd2_cas : out std_logic;
+--		sd2_ras : out std_logic;
+--		
+--		-- VGA
+--		vga_red 		: out std_logic_vector(5 downto 0);
+--		vga_green 	: out std_logic_vector(5 downto 0);
+--		vga_blue 	: out std_logic_vector(5 downto 0);
+--		
+--		vga_hsync 	: buffer std_logic;
+--		vga_vsync 	: buffer std_logic;
+--		
+--		vga_scandbl : in std_logic;
+--
+--		-- PS/2
+--		ps2k_clk : inout std_logic;
+--		ps2k_dat : inout std_logic;
+--		ps2m_clk : inout std_logic;
+--		ps2m_dat : inout std_logic;
+--		
+--		-- Audio
+--		aud_l : out std_logic;
+--		aud_r : out std_logic;
+--		
+--		-- RS232
+--		rs232_rxd : in std_logic;
+--		rs232_txd : out std_logic;
+--
+--		-- SD card interface
+--		sd_cs : out std_logic;
+--		sd_miso : in std_logic;
+--		sd_mosi : out std_logic;
+--		sd_clk : out std_logic;
+--		
+--		-- Power and LEDs
+--		power_button : in std_logic;
+--		power_hold : out std_logic := '1';
+--		leds : out std_logic_vector(3 downto 0);
+--		
+--		-- Joystick ports
+--		joy1 : in std_logic_vector(6 downto 0); -- Fire3, Fire2, Fire 1, Right, Left, Down, Up
+--		joy2 : in std_logic_vector(6 downto 0); -- Fire3, Fire2, Fire 1, Right, Left, Down, Up
+--
+--		-- Any remaining IOs yet to be assigned
+--		misc_ios_1 : out std_logic_vector(5 downto 0);
+--		misc_ios_21 : out std_logic_vector(1 downto 0);
+--		misc_ios_22 : out std_logic_vector(8 downto 0);
+--		misc_ios_3 : out std_logic
+--	);
+--end entity;
+
+
+entity target_top is
+  port
+    (
+      --////////////////////	Clock Input	 	////////////////////	 
+      CLOCK_50      : in std_logic;
+		--/////////////////// SD card interface ///////////////////
+		sd_cs : out std_logic;
+		sd_miso : in std_logic;
+		sd_mosi : out std_logic;
+		sd_clk : out std_logic;
+      --////////////////////////	Speaker		////////////////////////
+      AUDIO_L           : out std_logic;
+      AUDIO_R           : out std_logic;
+      --////////////////////	VGA		////////////////////////////
+      VGA_VS        : out std_logic;                        --	VGA H_SYNC
+      VGA_HS        : out std_logic;                        --	VGA V_SYNC
+      VGA_R         : out std_logic_vector(5 downto 0);     --	VGA Red[3:0]
+      VGA_G         : out std_logic_vector(5 downto 0);     --	VGA Green[3:0]
+      VGA_B         : out std_logic_vector(5 downto 0);      --	VGA Blue[3:0]
+
+      sd1_cs     : out std_logic;
+      sd2_cs     : out std_logic;
+
+		joy1 : in std_logic_vector(6 downto 0); -- Fire3, Fire2, Fire 1, Right, Left, Down, Up
+		joy2 : in std_logic_vector(6 downto 0); -- Fire3, Fire2, Fire 1, Right, Left, Down, Up
+
+--		-- Power and LEDs
+		power_button : in std_logic;
+		power_hold : out std_logic := '1';
+		leds : out std_logic_vector(3 downto 0);
+		reset_button : in std_logic
+
+      -- DATA0	    : in std_logic;                          --	DATA0
+  );    
+  
+end target_top;
+
+architecture SYN of target_top is
+
+-- Assigns pin location to ports on an entity.
+-- Declare the attribute or import its declaration from 
+-- altera.altera_syn_attributes
+attribute chip_pin : string;
+
+-- Board features
+
+attribute chip_pin of CLOCK_50 : signal is "152";
+attribute chip_pin of reset_button : signal is "181";
+--attribute chip_pin of led_out : signal is "233";
+
+-- SDRAM (2 distinct 8-bit wide chips)
+
+--attribute chip_pin of sd1_addr : signal is "83,69,82,81,80,78,99,110,63,64,65,68";
+--attribute chip_pin of sd1_data : signal is "109,103,111,93,100,106,107,108";
+--attribute chip_pin of sd1_ba : signal is "70,71";
+--attribute chip_pin of sdram1_clk : signal is "117";
+--attribute chip_pin of sd1_cke : signal is "84";
+--attribute chip_pin of sd1_dqm : signal is "87";
+attribute chip_pin of sd1_cs : signal is "72";
+--attribute chip_pin of sd1_we : signal is "88";
+--attribute chip_pin of sd1_cas : signal is "76";
+--attribute chip_pin of sd1_ras : signal is "73";
+
+--attribute chip_pin of sd2_addr : signal is "142,114,144,139,137,134,148,161,120,119,118,113";
+--attribute chip_pin of sd2_data : signal is "166,164,162,160,146,147,159,168";
+--attribute chip_pin of sd2_ba : signal is "126,127";
+--attribute chip_pin of sdram2_clk : signal is "186";
+--attribute chip_pin of sd2_cke : signal is "143";
+--attribute chip_pin of sd2_dqm : signal is "145";
+attribute chip_pin of sd2_cs : signal is "128";
+--attribute chip_pin of sd2_we : signal is "133";
+--attribute chip_pin of sd2_cas : signal is "132";
+--attribute chip_pin of sd2_ras : signal is "131";
+
+
+-- Video output via custom board
+
+attribute chip_pin of VGA_R : signal is "13, 9, 5, 240, 238, 236";
+attribute chip_pin of VGA_G : signal is "49, 45, 43, 39, 37, 18";
+attribute chip_pin of VGA_B : signal is "52, 50, 46, 44, 41, 38";
+
+attribute chip_pin of VGA_HS : signal is "51";
+attribute chip_pin of VGA_VS : signal is "55";
+
+-- Audio output via custom board
+
+attribute chip_pin of AUDIO_L : signal is "6";
+attribute chip_pin of AUDIO_R : signal is "22";
+
+-- PS/2 sockets on custom board
+
+--attribute chip_pin of ps2k_clk : signal is "235";
+--attribute chip_pin of ps2k_dat : signal is "237";
+--attribute chip_pin of ps2m_clk : signal is "239";
+--attribute chip_pin of ps2m_dat : signal is "4";
+
+-- RS232
+--attribute chip_pin of rs232_rxd : signal is "98";
+--attribute chip_pin of rs232_txd : signal is "112";
+
+-- SD card interface
+attribute chip_pin of sd_cs : signal is "185";
+attribute chip_pin of sd_miso : signal is "196";
+attribute chip_pin of sd_mosi : signal is "188";
+attribute chip_pin of sd_clk : signal is "194";
+
+
+-- Power and LEDs
+attribute chip_pin of power_hold : signal is "171";
+attribute chip_pin of power_button : signal is "94";
+
+attribute chip_pin of leds : signal is "173, 169, 167, 135";
+
+--attribute chip_pin of vga_scandbl : signal is "231";
+
+-- Free pins, not yet assigned
+
+--attribute chip_pin of misc_ios_1 : signal is "12,14,56,234,21,57";
+
+--attribute chip_pin of misc_ios_21 : signal is "226,232";
+--attribute chip_pin of misc_ios_22 : signal is "176,183,200,202,207,216,218,224,230";
+--attribute chip_pin of misc_ios_3 : signal is "95";
+
+attribute chip_pin of joy1 : signal is "201,203,214,217,219,221,223";
+attribute chip_pin of joy2 : signal is "184,182,177,197,195,189,187";
+
+  signal init       	: std_logic := '1';  
+  signal clock_27       : std_logic;
+  
+  signal clkrst_i       : from_CLKRST_t;
+  signal buttons_i      : from_BUTTONS_t;
+  signal switches_i     : from_SWITCHES_t;
+  signal leds_o         : to_LEDS_t;
+  signal inputs_i       : from_INPUTS_t;
+  signal flash_i        : from_FLASH_t;
+  signal flash_o        : to_FLASH_t;
+  signal sram_i			: from_SRAM_t;
+  signal sram_o			: to_SRAM_t;	
+  signal sdram_i        : from_SDRAM_t;
+  signal sdram_o        : to_SDRAM_t;
+  signal video_i        : from_VIDEO_t;
+  signal video_o        : to_VIDEO_t;
+  signal audio_i        : from_AUDIO_t;
+  signal audio_o        : to_AUDIO_t;
+  signal ser_i          : from_SERIAL_t;
+  signal ser_o          : to_SERIAL_t;
+  signal project_i      : from_PROJECT_IO_t;
+  signal project_o      : to_PROJECT_IO_t;
+  signal platform_i     : from_PLATFORM_IO_t;
+  signal platform_o     : to_PLATFORM_IO_t;
+  signal target_i       : from_TARGET_IO_t;
+  signal target_o       : to_TARGET_IO_t;
+
+  signal switches       : std_logic_vector(1 downto 0);
+  signal buttons        : std_logic_vector(1 downto 0);
+  
+--//********************
+
+begin
+
+--  SDRAM_nCS <= '1';   -- don't select SDRAM
+	sd1_cs<='1';
+	sd2_cs<='1';
+	sd_cs<='1'; -- don't select SD card either
+	switches<="00";
+	buttons <= power_button & reset_button;
+
+-- // Need Clock 50Mhz to Clock 27Mhz
+
+  BLK_CLOCKING : block
+  begin
+    clkrst_i.clk_ref <= CLOCK_50;
+  
+    GEN_PLL : if PACE_HAS_PLL generate
+    
+      pll_50_inst : entity work.pllclk_ez --entity work.pllclk_ez  --entity work.pll
+        port map
+        (
+          inclk0  => CLOCK_50,
+          c0      => clkrst_i.clk(0),  --30Mhz
+          c1      => clkrst_i.clk(1),  --40Mhz
+          c3      => clock_27,         --27.27Mhz
+          c4      => clkrst_i.clk(2)   --18.46Mhz
+        );
+
+    end generate GEN_PLL;
+    
+    GEN_NO_PLL : if not PACE_HAS_PLL generate
+   
+      -- feed input clocks into PACE core
+      clkrst_i.clk(0) <= CLOCK_50;
+      clkrst_i.clk(1) <= clock_27;
+        
+    end generate GEN_NO_PLL;
+      
+  end block BLK_CLOCKING;
+	
+  -- FPGA STARTUP
+	-- should extend power-on reset if registers init to '0'
+	process (CLOCK_50)
+		variable count : std_logic_vector (11 downto 0) := (others => '0');
+	begin
+		if rising_edge(CLOCK_50) then
+			if count = X"FFF" then
+				init <= '0';
+			else
+				count := count + 1;
+				init <= '1';
+			end if;
+		end if;
+	end process;
+
+  clkrst_i.arst <= init;
+  clkrst_i.arst_n <= not clkrst_i.arst;
+
+  GEN_RESETS : for i in 0 to 3 generate
+
+    process (clkrst_i.clk(i), clkrst_i.arst)
+      variable rst_r : std_logic_vector(2 downto 0) := (others => '0');
+    begin
+      if clkrst_i.arst = '1' then
+        rst_r := (others => '1');
+      elsif rising_edge(clkrst_i.clk(i)) then
+        rst_r := rst_r(rst_r'left-1 downto 0) & '0';
+      end if;
+      clkrst_i.rst(i) <= rst_r(rst_r'left);
+    end process;
+
+  end generate GEN_RESETS;
+
+      -- inputs
+
+       switches_i(0) <= switches(0);
+       switches_i(1) <= switches(1);
+
+       GEN_NO_JAMMA : if PACE_JAMMA = PACE_JAMMA_NONE generate
+		inputs_i.jamma_n.coin(1) <= buttons(0);
+		inputs_i.jamma_n.p(1).start <= buttons(1);
+		inputs_i.jamma_n.p(1).up <= joy1(2);
+		inputs_i.jamma_n.p(1).down <= joy1(3);
+		inputs_i.jamma_n.p(1).left <= joy1(4);
+		inputs_i.jamma_n.p(1).right <= joy1(5);
+		inputs_i.jamma_n.p(1).button(1) <= joy1(1);
+		inputs_i.jamma_n.p(1).button(2) <= joy1(0);
+		inputs_i.jamma_n.p(1).button(3) <= joy1(6);
+		inputs_i.jamma_n.p(1).button(4) <= '1';
+		inputs_i.jamma_n.p(1).button(5) <= '1';
+        end generate GEN_NO_JAMMA;
+  
+	-- not currently wired to any inputs
+	inputs_i.jamma_n.coin_cnt <= (others => '1');
+	inputs_i.jamma_n.coin(2) <= '1';
+	inputs_i.jamma_n.p(2).start <= '1';
+	inputs_i.jamma_n.p(2).up <= '1';
+	inputs_i.jamma_n.p(2).down <= '1';
+	inputs_i.jamma_n.p(2).left <= '1';
+	inputs_i.jamma_n.p(2).right <= '1';
+	inputs_i.jamma_n.p(2).button <= (others => '1');
+	inputs_i.jamma_n.service <= '1';
+	inputs_i.jamma_n.tilt <= '1';
+	inputs_i.jamma_n.test <= '1';
+		
+  BLK_VIDEO : block
+  begin
+
+    video_i.clk <= clkrst_i.clk(1);	-- by convention
+    video_i.clk_ena <= '1';
+    video_i.reset <= clkrst_i.rst(1);
+    
+    VGA_R <= video_o.rgb.r(video_o.rgb.r'left downto video_o.rgb.r'left-5);
+    VGA_G <= video_o.rgb.g(video_o.rgb.g'left downto video_o.rgb.g'left-5);
+    VGA_B <= video_o.rgb.b(video_o.rgb.b'left downto video_o.rgb.b'left-5);
+    VGA_HS <= video_o.hsync;
+    VGA_VS <= video_o.vsync;
+ 
+  end block BLK_VIDEO;
+
+  BLK_AUDIO : block
+  begin
+  
+    dacl : entity work.sigma_delta_dac
+      port map (
+        clk     => CLOCK_50,
+        din     => audio_o.ldata(15 downto 8),
+        dout    => AUDIO_L
+      );        
+
+    dacr : entity work.sigma_delta_dac
+      port map (
+        clk     => CLOCK_50,
+        din     => audio_o.rdata(15 downto 8),
+        dout    => AUDIO_R
+      );        
+
+  end block BLK_AUDIO;
+ 
+ pace_inst : entity work.pace                                            
+   port map
+   (
+     -- clocks and resets
+     clkrst_i					=> clkrst_i,
+
+     -- misc inputs and outputs
+     buttons_i         => buttons_i,
+     switches_i        => switches_i,
+     leds_o            => open,
+     
+     -- controller inputs
+     inputs_i          => inputs_i,
+
+     	-- external ROM/RAM
+     flash_i           => flash_i,
+     flash_o           => flash_o,
+     sram_i        		=> sram_i,
+     sram_o        		=> sram_o,
+     sdram_i           => sdram_i,
+     sdram_o           => sdram_o,
+  
+      -- VGA video
+      video_i           => video_i,
+      video_o           => video_o,
+      
+      -- sound
+      audio_i           => audio_i,
+      audio_o           => audio_o,
+
+      -- SPI (flash)
+      spi_i.din         => '0',
+      spi_o             => open,
+  
+      -- serial
+      ser_i             => ser_i,
+      ser_o             => ser_o,
+      
+      -- custom i/o
+      project_i         => project_i,
+      project_o         => project_o,
+      platform_i        => platform_i,
+      platform_o        => platform_o,
+      target_i          => target_i,
+      target_o          => target_o
+    );
+end SYN;
diff --git a/sw/src/target/retroramblings_c3/target_top.vhd.bak b/sw/src/target/retroramblings_c3/target_top.vhd.bak
new file mode 100644
index 0000000..14c573c
--- /dev/null
+++ b/sw/src/target/retroramblings_c3/target_top.vhd.bak
@@ -0,0 +1,279 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.pace_pkg.all;
+use work.sdram_pkg.all;
+use work.video_controller_pkg.all;
+use work.maple_pkg.all;
+use work.gamecube_pkg.all;
+use work.project_pkg.all;
+use work.platform_pkg.all;
+use work.target_pkg.all;
+
+entity target_top is
+  port
+    (
+      --////////////////////	Clock Input	 	////////////////////	 
+      CLOCK_50      : in std_logic_vector(1 downto 0);                       --	50 MHz
+      --////////////////////////	SPI	////////////////////////
+      SPI_SCK : in std_logic;
+      SPI_DI : in std_logic;
+      SPI_DO : out std_logic;
+      CONF_DATA0 : in std_logic;
+      --////////////////////////	Speaker		////////////////////////
+      AUDIO_L           : out std_logic;
+      AUDIO_R           : out std_logic;
+      --////////////////////	VGA		////////////////////////////
+      VGA_VS        : out std_logic;                        --	VGA H_SYNC
+      VGA_HS        : out std_logic;                        --	VGA V_SYNC
+      VGA_R         : out std_logic_vector(5 downto 0);     --	VGA Red[3:0]
+      VGA_G         : out std_logic_vector(5 downto 0);     --	VGA Green[3:0]
+      VGA_B         : out std_logic_vector(5 downto 0);      --	VGA Blue[3:0]
+
+      SDRAM_nCS     : out std_logic
+
+      -- DATA0	    : in std_logic;                          --	DATA0
+  );    
+  
+end target_top;
+
+architecture SYN of target_top is
+
+  component user_io
+    port ( SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic;
+           SPI_MISO : out std_logic;
+           JOY0 :     out std_logic_vector(5 downto 0);
+           SWITCHES : out std_logic_vector(1 downto 0);
+           BUTTONS : out std_logic_vector(1 downto 0);
+           CORE_TYPE : in std_logic_vector(7 downto 0)
+           );
+   end component user_io;
+
+  signal init       	: std_logic := '1';  
+  signal clock_27       : std_logic;
+  
+  signal clkrst_i       : from_CLKRST_t;
+  signal buttons_i      : from_BUTTONS_t;
+  signal switches_i     : from_SWITCHES_t;
+  signal leds_o         : to_LEDS_t;
+  signal inputs_i       : from_INPUTS_t;
+  signal flash_i        : from_FLASH_t;
+  signal flash_o        : to_FLASH_t;
+  signal sram_i			: from_SRAM_t;
+  signal sram_o			: to_SRAM_t;	
+  signal sdram_i        : from_SDRAM_t;
+  signal sdram_o        : to_SDRAM_t;
+  signal video_i        : from_VIDEO_t;
+  signal video_o        : to_VIDEO_t;
+  signal audio_i        : from_AUDIO_t;
+  signal audio_o        : to_AUDIO_t;
+  signal ser_i          : from_SERIAL_t;
+  signal ser_o          : to_SERIAL_t;
+  signal project_i      : from_PROJECT_IO_t;
+  signal project_o      : to_PROJECT_IO_t;
+  signal platform_i     : from_PLATFORM_IO_t;
+  signal platform_o     : to_PLATFORM_IO_t;
+  signal target_i       : from_TARGET_IO_t;
+  signal target_o       : to_TARGET_IO_t;
+
+  signal joystick       : std_logic_vector(5 downto 0);
+  signal switches       : std_logic_vector(1 downto 0);
+  signal buttons        : std_logic_vector(1 downto 0);
+  
+--//********************
+
+begin
+
+  SDRAM_nCS <= '1';   -- don't select SDRAM
+
+-- // Need Clock 50Mhz to Clock 27Mhz
+
+  BLK_CLOCKING : block
+  begin
+    clkrst_i.clk_ref <= CLOCK_50(0);
+  
+    GEN_PLL : if PACE_HAS_PLL generate
+    
+      pll_50_inst : entity work.pllclk_ez --entity work.pllclk_ez  --entity work.pll
+        port map
+        (
+          inclk0  => CLOCK_50(0),
+          c0      => clkrst_i.clk(0),  --30Mhz
+          c1      => clkrst_i.clk(1),  --40Mhz
+          c3      => clock_27,         --27.27Mhz
+          c4      => clkrst_i.clk(2)   --18.46Mhz
+        );
+
+    end generate GEN_PLL;
+    
+    GEN_NO_PLL : if not PACE_HAS_PLL generate
+   
+      -- feed input clocks into PACE core
+      clkrst_i.clk(0) <= CLOCK_50(0);
+      clkrst_i.clk(1) <= clock_27;
+        
+    end generate GEN_NO_PLL;
+      
+  end block BLK_CLOCKING;
+	
+  -- FPGA STARTUP
+	-- should extend power-on reset if registers init to '0'
+	process (CLOCK_50(0))
+		variable count : std_logic_vector (11 downto 0) := (others => '0');
+	begin
+		if rising_edge(CLOCK_50(0)) then
+			if count = X"FFF" then
+				init <= '0';
+			else
+				count := count + 1;
+				init <= '1';
+			end if;
+		end if;
+	end process;
+
+  clkrst_i.arst <= init;
+  clkrst_i.arst_n <= not clkrst_i.arst;
+
+  GEN_RESETS : for i in 0 to 3 generate
+
+    process (clkrst_i.clk(i), clkrst_i.arst)
+      variable rst_r : std_logic_vector(2 downto 0) := (others => '0');
+    begin
+      if clkrst_i.arst = '1' then
+        rst_r := (others => '1');
+      elsif rising_edge(clkrst_i.clk(i)) then
+        rst_r := rst_r(rst_r'left-1 downto 0) & '0';
+      end if;
+      clkrst_i.rst(i) <= rst_r(rst_r'left);
+    end process;
+
+  end generate GEN_RESETS;
+
+      -- inputs
+      user_io_d : user_io
+        port map
+        (
+          SPI_CLK => SPI_SCK,
+          SPI_SS_IO => CONF_DATA0,
+          SPI_MISO => SPI_DO,
+          SPI_MOSI => SPI_DI,
+          JOY0 => joystick,
+          SWITCHES => switches,
+          BUTTONS => buttons,
+          CORE_TYPE => X"a2"            -- PACE core type
+          );
+
+       switches_i(0) <= switches(0);
+       switches_i(1) <= switches(1);
+
+       GEN_NO_JAMMA : if PACE_JAMMA = PACE_JAMMA_NONE generate
+		inputs_i.jamma_n.coin(1) <= not buttons(0);
+		inputs_i.jamma_n.p(1).start <= not buttons(1);
+		inputs_i.jamma_n.p(1).up <= not joystick(3);
+		inputs_i.jamma_n.p(1).down <= not joystick(2);
+		inputs_i.jamma_n.p(1).left <= not joystick(1);
+		inputs_i.jamma_n.p(1).right <= not joystick(0);
+		inputs_i.jamma_n.p(1).button(1) <= not joystick(4); 
+		inputs_i.jamma_n.p(1).button(2) <= not joystick(5); 
+		inputs_i.jamma_n.p(1).button(3) <= '1';
+		inputs_i.jamma_n.p(1).button(4) <= '1';
+		inputs_i.jamma_n.p(1).button(5) <= '1';
+        end generate GEN_NO_JAMMA;
+  
+	-- not currently wired to any inputs
+	inputs_i.jamma_n.coin_cnt <= (others => '1');
+	inputs_i.jamma_n.coin(2) <= '1';
+	inputs_i.jamma_n.p(2).start <= '1';
+	inputs_i.jamma_n.p(2).up <= '1';
+	inputs_i.jamma_n.p(2).down <= '1';
+	inputs_i.jamma_n.p(2).left <= '1';
+	inputs_i.jamma_n.p(2).right <= '1';
+	inputs_i.jamma_n.p(2).button <= (others => '1');
+	inputs_i.jamma_n.service <= '1';
+	inputs_i.jamma_n.tilt <= '1';
+	inputs_i.jamma_n.test <= '1';
+		
+  BLK_VIDEO : block
+  begin
+
+    video_i.clk <= clkrst_i.clk(1);	-- by convention
+    video_i.clk_ena <= '1';
+    video_i.reset <= clkrst_i.rst(1);
+    
+    VGA_R <= video_o.rgb.r(video_o.rgb.r'left downto video_o.rgb.r'left-5);
+    VGA_G <= video_o.rgb.g(video_o.rgb.g'left downto video_o.rgb.g'left-5);
+    VGA_B <= video_o.rgb.b(video_o.rgb.b'left downto video_o.rgb.b'left-5);
+    VGA_HS <= video_o.hsync;
+    VGA_VS <= video_o.vsync;
+ 
+  end block BLK_VIDEO;
+
+  BLK_AUDIO : block
+  begin
+  
+    dacl : entity work.sigma_delta_dac
+      port map (
+        clk     => CLOCK_50(0),
+        din     => audio_o.ldata(15 downto 8),
+        dout    => AUDIO_L
+      );        
+
+    dacr : entity work.sigma_delta_dac
+      port map (
+        clk     => CLOCK_50(0),
+        din     => audio_o.rdata(15 downto 8),
+        dout    => AUDIO_R
+      );        
+
+  end block BLK_AUDIO;
+ 
+ pace_inst : entity work.pace                                            
+   port map
+   (
+     -- clocks and resets
+     clkrst_i					=> clkrst_i,
+
+     -- misc inputs and outputs
+     buttons_i         => buttons_i,
+     switches_i        => switches_i,
+     leds_o            => open,
+     
+     -- controller inputs
+     inputs_i          => inputs_i,
+
+     	-- external ROM/RAM
+     flash_i           => flash_i,
+     flash_o           => flash_o,
+     sram_i        		=> sram_i,
+     sram_o        		=> sram_o,
+     sdram_i           => sdram_i,
+     sdram_o           => sdram_o,
+  
+      -- VGA video
+      video_i           => video_i,
+      video_o           => video_o,
+      
+      -- sound
+      audio_i           => audio_i,
+      audio_o           => audio_o,
+
+      -- SPI (flash)
+      spi_i.din         => '0',
+      spi_o             => open,
+  
+      -- serial
+      ser_i             => ser_i,
+      ser_o             => ser_o,
+      
+      -- custom i/o
+      project_i         => project_i,
+      project_o         => project_o,
+      platform_i        => platform_i,
+      platform_o        => platform_o,
+      target_i          => target_i,
+      target_o          => target_o
+    );
+end SYN;
diff --git a/sw/synth/platform/pacman/chameleon64/pacman.qpf b/sw/synth/platform/pacman/chameleon64/pacman.qpf
new file mode 100644
index 0000000..becf671
--- /dev/null
+++ b/sw/synth/platform/pacman/chameleon64/pacman.qpf
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2005 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic       
+# functions, and any output files any of the foregoing           
+# (including device programming or simulation files), and any    
+# associated documentation or information are expressly subject  
+# to the terms and conditions of the Altera Program License      
+# Subscription Agreement, Altera MegaCore Function License       
+# Agreement, or other applicable license agreement, including,   
+# without limitation, that your use is for the sole purpose of   
+# programming logic devices manufactured by Altera and sold by   
+# Altera or its authorized distributors.  Please refer to the    
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "5.0"
+DATE = "19:21:54  August 25, 2005"
+
+
+# Revisions
+
+PROJECT_REVISION = "pacman"
diff --git a/sw/synth/platform/pacman/chameleon64/pacman.qsf b/sw/synth/platform/pacman/chameleon64/pacman.qsf
new file mode 100644
index 0000000..d5cc83b
--- /dev/null
+++ b/sw/synth/platform/pacman/chameleon64/pacman.qsf
@@ -0,0 +1,322 @@
+# copyright (c) 1991-2005 altera corporation
+# your use of altera corporation's design tools, logic functions 
+# and other software and tools, and its ampp partner logic       
+# functions, and any output files any of the foregoing           
+# (including device programming or simulation files), and any    
+# associated documentation or information are expressly subject  
+# to the terms and conditions of the altera program license      
+# subscription agreement, altera megacore function license       
+# agreement, or other applicable license agreement, including,   
+# without limitation, that your use is for the sole purpose of   
+# programming logic devices manufactured by altera and sold by   
+# altera or its authorized distributors.  please refer to the    
+# applicable agreement for further details.
+
+
+# the default values for assignments are stored in the file
+#		pacman_assignment_defaults.qdf
+# if this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# altera recommends that you do not modify this file. this
+# file is updated automatically by the quartus ii software
+# and any changes you make may be lost or overwritten.
+
+
+# project-wide assignments
+# ========================
+set_global_assignment -name LAST_QUARTUS_VERSION "12.0 SP1"
+
+# pin & location assignments
+# ==========================
+
+# analysis & synthesis assignments
+# ================================
+set_global_assignment -name TOP_LEVEL_ENTITY target_top
+
+# fitter assignments
+# ==================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+# assembler assignments
+# =====================
+
+set_global_assignment -name SEED 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+
+
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_location_assignment PIN_111 -to red[0]
+set_location_assignment PIN_110 -to red[1]
+set_location_assignment PIN_106 -to red[2]
+set_location_assignment PIN_105 -to red[3]
+set_location_assignment PIN_104 -to red[4]
+set_location_assignment PIN_103 -to grn[0]
+set_location_assignment PIN_101 -to grn[1]
+set_location_assignment PIN_100 -to grn[2]
+set_location_assignment PIN_99 -to grn[3]
+set_location_assignment PIN_98 -to grn[4]
+set_location_assignment PIN_112 -to blu[0]
+set_location_assignment PIN_133 -to blu[1]
+set_location_assignment PIN_135 -to blu[2]
+set_location_assignment PIN_136 -to blu[3]
+set_location_assignment PIN_137 -to blu[4]
+set_location_assignment PIN_44 -to sd_clk
+set_location_assignment PIN_42 -to sd_addr[12]
+set_location_assignment PIN_33 -to sd_addr[11]
+set_location_assignment PIN_144 -to sd_addr[10]
+set_location_assignment PIN_31 -to sd_addr[9]
+set_location_assignment PIN_28 -to sd_addr[8]
+set_location_assignment PIN_11 -to sd_addr[7]
+set_location_assignment PIN_10 -to sd_addr[6]
+set_location_assignment PIN_8 -to sd_addr[5]
+set_location_assignment PIN_7 -to sd_addr[4]
+set_location_assignment PIN_30 -to sd_addr[3]
+set_location_assignment PIN_32 -to sd_addr[2]
+set_location_assignment PIN_6 -to sd_addr[1]
+set_location_assignment PIN_4 -to sd_addr[0]
+set_location_assignment PIN_39 -to sd_ba_0
+set_location_assignment PIN_143 -to sd_ba_1
+set_location_assignment PIN_50 -to sd_we_n
+set_location_assignment PIN_43 -to sd_ras_n
+set_location_assignment PIN_46 -to sd_cas_n
+set_location_assignment PIN_76 -to sd_data[15]
+set_location_assignment PIN_77 -to sd_data[14]
+set_location_assignment PIN_72 -to sd_data[13]
+set_location_assignment PIN_69 -to sd_data[12]
+set_location_assignment PIN_67 -to sd_data[11]
+set_location_assignment PIN_65 -to sd_data[10]
+set_location_assignment PIN_60 -to sd_data[9]
+set_location_assignment PIN_58 -to sd_data[8]
+set_location_assignment PIN_59 -to sd_data[7]
+set_location_assignment PIN_64 -to sd_data[6]
+set_location_assignment PIN_66 -to sd_data[5]
+set_location_assignment PIN_68 -to sd_data[4]
+set_location_assignment PIN_71 -to sd_data[3]
+set_location_assignment PIN_79 -to sd_data[2]
+set_location_assignment PIN_80 -to sd_data[1]
+set_location_assignment PIN_83 -to sd_data[0]
+set_location_assignment PIN_51 -to sd_ldqm
+set_location_assignment PIN_49 -to sd_udqm
+set_location_assignment PIN_25 -to clk8
+set_location_assignment PIN_142 -to nHSync
+set_location_assignment PIN_141 -to nVSync
+set_location_assignment PIN_87 -to mux_clk
+set_location_assignment PIN_119 -to mux[0]
+set_location_assignment PIN_115 -to mux[1]
+set_location_assignment PIN_114 -to mux[2]
+set_location_assignment PIN_113 -to mux[3]
+set_location_assignment PIN_125 -to mux_d[0]
+set_location_assignment PIN_121 -to mux_d[1]
+set_location_assignment PIN_120 -to mux_d[2]
+set_location_assignment PIN_132 -to mux_d[3]
+set_location_assignment PIN_126 -to mux_q[0]
+set_location_assignment PIN_127 -to mux_q[1]
+set_location_assignment PIN_128 -to mux_q[2]
+set_location_assignment PIN_129 -to mux_q[3]
+set_location_assignment PIN_86 -to sigmaL
+set_location_assignment PIN_85 -to sigmaR
+set_location_assignment PIN_89 -to dotclock_n
+set_location_assignment PIN_88 -to phi2_n
+set_location_assignment PIN_90 -to io_ef
+set_location_assignment PIN_91 -to rom_lh
+set_location_assignment PIN_13 -to spi_miso
+set_location_assignment PIN_22 -to mmc_cd_n
+set_location_assignment PIN_24 -to mmc_wp
+set_location_assignment PIN_52 -to usart_tx
+set_location_assignment PIN_53 -to usart_clk
+set_location_assignment PIN_54 -to usart_rts
+set_location_assignment PIN_55 -to usart_cts
+set_location_assignment PIN_23 -to freeze_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[12] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[0] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[11] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[10] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[9] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[8] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[7] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[6] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[5] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[4] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[3] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[2] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_addr[1] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_ba_0 -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_ba_1 -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_cas_n -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_clk -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_ldqm -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_ras_n -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_udqm -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_we_n -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[15] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[15] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[14] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[14] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[13] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[13] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[12] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[12] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[11] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[11] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[10] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[10] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[9] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[9] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[8] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[8] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[7] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[6] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[5] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[4] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[3] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[2] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[1] -entity chameleon_example_io
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to sd_data[0] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[7] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[6] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[5] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[4] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[3] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[2] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[1] -entity chameleon_example_io
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to sd_data[0] -entity chameleon_example_io
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sigmaL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sigmaR
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nHSync
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nVSync
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to red[*]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to grn[*]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to blu[*]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mux_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mux[*]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mux_d[*]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to mux_q[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to mux_clk -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to mux[*] -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to mux_d[*] -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to mux_q[*] -entity chameleon_example_io
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_we_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_cas_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_ras_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_ba_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_ba_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_ldqm
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_udqm
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_addr[*]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sd_data[*]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sd_clk -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sd_we_n -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sd_cas_n -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sd_ras_n -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sd_ba_0 -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sd_ba_1 -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sd_ldqm -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sd_udqm -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sd_addr[*] -entity chameleon_example_io
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sd_data[*] -entity chameleon_example_io
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity chameleon_example_io -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity chameleon_example_io -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -entity chameleon_example_io -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity chameleon_example_io -section_id Top
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/target_top.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/target_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/custom_io.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/chameleon_phi_clock_e.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/chameleon_phi_clock_a.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/chameleon_led.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/chameleon_io.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/chameleon_docking_station.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/chameleon_cdtv_remote.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/chameleon_c64_joykeyb.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/chameleon_buttons.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/chameleon_1mhz.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/chameleon64/chameleon_1khz.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/pace_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/pace_pkg_body.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/stubs/sdram_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller_pkg_body.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/tilemapctl_e.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/bitmapctl_e.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_pkg_body.vhd
+set_global_assignment -name VHDL_FILE project_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/platform_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/pll.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/sprom.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/dpram.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/spram.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/clk_div.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/ps2/ps2kbd_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/ps2/ps2kbd.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80se.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/Z80.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/altera_mem.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pengo/tilemapctl.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/spritereg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pengo/spritectl.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_array.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_mixer.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/Graphics.VHD
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/InputMapper.VHD
+set_global_assignment -name VHDL_FILE ../../../../src/pace/Inputs.VHD
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/Pacman_Interrupts.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/Pacman_vramMapper.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/platform.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/pacsnd.Vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/sound.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/pace.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/gamecube/gamecube_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/load_upcounter.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/conversion.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_read2.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_write.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/mfifo.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_bus.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_joy.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/toys/led_chaser.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/toys/pwm_chaser.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/toys/pwmout.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/sound/sigma_delta_dac.vhd
+set_global_assignment -name QIP_FILE pllclk_ez.qip
+set_global_assignment -name SIGNALTAP_FILE stp1.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/sw/synth/platform/pacman/chameleon64/pllclk_ez.cmp b/sw/synth/platform/pacman/chameleon64/pllclk_ez.cmp
new file mode 100644
index 0000000..5bc3595
--- /dev/null
+++ b/sw/synth/platform/pacman/chameleon64/pllclk_ez.cmp
@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pllclk_ez
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
diff --git a/sw/synth/platform/pacman/chameleon64/pllclk_ez.ppf b/sw/synth/platform/pacman/chameleon64/pllclk_ez.ppf
new file mode 100644
index 0000000..7e30f66
--- /dev/null
+++ b/sw/synth/platform/pacman/chameleon64/pllclk_ez.ppf
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pllclk_ez" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/sw/synth/platform/pacman/chameleon64/pllclk_ez.qip b/sw/synth/platform/pacman/chameleon64/pllclk_ez.qip
new file mode 100644
index 0000000..82a306f
--- /dev/null
+++ b/sw/synth/platform/pacman/chameleon64/pllclk_ez.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pllclk_ez.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.ppf"]
diff --git a/sw/synth/platform/pacman/chameleon64/pllclk_ez.vhd b/sw/synth/platform/pacman/chameleon64/pllclk_ez.vhd
new file mode 100644
index 0000000..9cb8a6e
--- /dev/null
+++ b/sw/synth/platform/pacman/chameleon64/pllclk_ez.vhd
@@ -0,0 +1,495 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pllclk_ez.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.0 Build 232 07/05/2012 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pllclk_ez IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pllclk_ez;
+
+
+ARCHITECTURE SYN OF pllclk_ez IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC ;
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire9_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire9_bv(0 DOWNTO 0) <= "0";
+	sub_wire9    <= To_stdlogicvector(sub_wire9_bv);
+	sub_wire5    <= sub_wire0(3);
+	sub_wire4    <= sub_wire0(4);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c0    <= sub_wire2;
+	c2    <= sub_wire3;
+	c4    <= sub_wire4;
+	c3    <= sub_wire5;
+	locked    <= sub_wire6;
+	sub_wire7    <= inclk0;
+	sub_wire8    <= sub_wire9(0 DOWNTO 0) & sub_wire7;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 4,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 15,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 1,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 5,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 2,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 25,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 32,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 109,
+		clk3_phase_shift => "0",
+		clk4_divide_by => 8000000,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 18449999,
+		clk4_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 125000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pllclk_ez",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire8,
+		clk => sub_wire0,
+		locked => sub_wire6
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "30.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "27.250000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "18.450001"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "8.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "30.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "27.25000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "18.45000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pllclk_ez.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "15"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "32"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "109"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "8000000"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "18449999"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "125000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/sw/synth/platform/pacman/chameleon64/project_pkg.vhd b/sw/synth/platform/pacman/chameleon64/project_pkg.vhd
new file mode 100644
index 0000000..d323f57
--- /dev/null
+++ b/sw/synth/platform/pacman/chameleon64/project_pkg.vhd
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.pace_pkg.all;
+use work.target_pkg.all;
+use work.video_controller_pkg.all;
+
+package project_pkg is
+
+	--  
+	-- PACE constants which *MUST* be defined
+	--
+	
+  -- Reference clock is 16MHz
+  constant PACE_HAS_PLL						: boolean := true;
+  --constant PACE_HAS_SRAM                    : boolean := true;
+  constant PACE_HAS_SDRAM                   : boolean := false;
+  constant PACE_HAS_FLASH                   : boolean := false;
+  constant PACE_HAS_SERIAL                  : boolean := false;
+  
+  constant PACE_JAMMA	                    : PACEJamma_t := PACE_JAMMA_NONE;
+
+  constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_VGA_800x600_60Hz;
+  constant PACE_CLK0_DIVIDE_BY        		: natural := 5;
+  constant PACE_CLK0_MULTIPLY_BY      		: natural := 3;   -- 16*15/8 = 30MHz
+  constant PACE_CLK1_DIVIDE_BY        		: natural := 5;
+  constant PACE_CLK1_MULTIPLY_BY      		: natural := 4;   -- 16*5/2 = 40MHz
+  constant PACE_VIDEO_H_SCALE         		: integer := 2;
+  constant PACE_VIDEO_V_SCALE         		: integer := 2;
+  constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '1';
+  constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '1';
+
+  constant PACE_VIDEO_BORDER_RGB            : RGB_t := RGB_GREEN;
+
+  constant PACE_HAS_OSD                     : boolean := false;
+  constant PACE_OSD_XPOS                    : natural := 0;
+  constant PACE_OSD_YPOS                    : natural := 0;
+
+        -- Pacman-specific constants
+
+  constant PACMAN_ROM_IN_SRAM               : boolean := false;
+  constant PACMAN_USE_INTERNAL_WRAM         : boolean := true;
+  constant PACMAN_USE_VIDEO_VBLANK          : boolean := true;
+  
+        -- derived
+  constant PACE_HAS_SRAM                    : boolean := PACMAN_ROM_IN_SRAM or 
+                                                 not PACMAN_USE_INTERNAL_WRAM;
+
+  type from_PROJECT_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+  type to_PROJECT_IO_t is record
+    not_used  : std_logic;
+  end record;
+end;
diff --git a/sw/synth/platform/pacman/mist/Makefile b/sw/synth/platform/pacman/mist/Makefile
new file mode 100644
index 0000000..7d205e3
--- /dev/null
+++ b/sw/synth/platform/pacman/mist/Makefile
@@ -0,0 +1,47 @@
+# fpga makefile
+# 2012, rok.krajnc@gmail.com
+
+
+### programs ###
+MAP=quartus_map
+FIT=quartus_fit
+ASM=quartus_asm
+PGM=quartus_pgm
+
+
+### project ###
+PROJECT=pacman
+
+
+### build rules ###
+
+# all
+all:
+	@echo Making FPGA programming files ...
+	@make map
+	@make fit
+	@make asm
+
+map:
+	@echo Running mapper ...
+	@$(MAP) $(PROJECT)
+
+fit:
+	@echo Running fitter ...
+	@$(FIT) $(PROJECT)
+
+asm:
+	@echo Running assembler ...
+	@$(ASM) $(PROJECT)
+
+run: 
+	@$(PGM) -c USB-Blaster -m jtag -o "p;$(PROJECT).sof"
+
+
+# clean
+clean:
+	@echo clean
+	@rm -rf ./out/
+	@rm -rf ./db/
+	@rm -rf ./incremental_db/
+
diff --git a/sw/synth/platform/pacman/mist/pacman.qpf b/sw/synth/platform/pacman/mist/pacman.qpf
new file mode 100644
index 0000000..becf671
--- /dev/null
+++ b/sw/synth/platform/pacman/mist/pacman.qpf
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2005 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic       
+# functions, and any output files any of the foregoing           
+# (including device programming or simulation files), and any    
+# associated documentation or information are expressly subject  
+# to the terms and conditions of the Altera Program License      
+# Subscription Agreement, Altera MegaCore Function License       
+# Agreement, or other applicable license agreement, including,   
+# without limitation, that your use is for the sole purpose of   
+# programming logic devices manufactured by Altera and sold by   
+# Altera or its authorized distributors.  Please refer to the    
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "5.0"
+DATE = "19:21:54  August 25, 2005"
+
+
+# Revisions
+
+PROJECT_REVISION = "pacman"
diff --git a/sw/synth/platform/pacman/mist/pacman.qsf b/sw/synth/platform/pacman/mist/pacman.qsf
new file mode 100644
index 0000000..86e3e06
--- /dev/null
+++ b/sw/synth/platform/pacman/mist/pacman.qsf
@@ -0,0 +1,206 @@
+# copyright (c) 1991-2005 altera corporation
+# your use of altera corporation's design tools, logic functions 
+# and other software and tools, and its ampp partner logic       
+# functions, and any output files any of the foregoing           
+# (including device programming or simulation files), and any    
+# associated documentation or information are expressly subject  
+# to the terms and conditions of the altera program license      
+# subscription agreement, altera megacore function license       
+# agreement, or other applicable license agreement, including,   
+# without limitation, that your use is for the sole purpose of   
+# programming logic devices manufactured by altera and sold by   
+# altera or its authorized distributors.  please refer to the    
+# applicable agreement for further details.
+
+
+# the default values for assignments are stored in the file
+#		pacman_assignment_defaults.qdf
+# if this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# altera recommends that you do not modify this file. this
+# file is updated automatically by the quartus ii software
+# and any changes you make may be lost or overwritten.
+
+
+# project-wide assignments
+# ========================
+set_global_assignment -name LAST_QUARTUS_VERSION 12.1
+
+# pin & location assignments
+# ==========================
+
+# analysis & synthesis assignments
+# ================================
+set_global_assignment -name TOP_LEVEL_ENTITY target_top
+
+# fitter assignments
+# ==================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+# assembler assignments
+# =====================
+
+set_global_assignment -name SEED 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27[0]
+set_location_assignment PIN_55 -to CLOCK_27[1]
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_46 -to UART_TX
+set_location_assignment PIN_31 -to UART_RX
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name VHDL_FILE ../../../../src/pace/pace_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/pace_pkg_body.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/stubs/sdram_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller_pkg_body.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/tilemapctl_e.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/bitmapctl_e.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_pkg_body.vhd
+set_global_assignment -name VHDL_FILE project_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/platform_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/mist/target_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/pll.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/sprom.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/dpram.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/spram.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/clk_div.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/ps2/ps2kbd_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/ps2/ps2kbd.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80se.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/Z80.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/altera_mem.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pengo/tilemapctl.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/spritereg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pengo/spritectl.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_array.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_mixer.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/Graphics.VHD
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/InputMapper.VHD
+set_global_assignment -name VHDL_FILE ../../../../src/pace/Inputs.VHD
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/Pacman_Interrupts.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/Pacman_vramMapper.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/platform.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/pacsnd.Vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/sound.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/pace.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/gamecube/gamecube_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/load_upcounter.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/conversion.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_read2.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_write.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/mfifo.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_bus.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_joy.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/toys/led_chaser.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/toys/pwm_chaser.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/toys/pwmout.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/mist/target_top.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/mist/custom_io.vhd
+set_global_assignment -name VERILOG_FILE ../../../../src/target/mist/user_io.v
+set_global_assignment -name VHDL_FILE ../../../../src/component/sound/sigma_delta_dac.vhd
+set_global_assignment -name QIP_FILE pllclk_ez.qip
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/sw/synth/platform/pacman/mist/pacman.qws b/sw/synth/platform/pacman/mist/pacman.qws
new file mode 100644
index 0000000..b5dd20e
Binary files /dev/null and b/sw/synth/platform/pacman/mist/pacman.qws differ
diff --git a/sw/synth/platform/pacman/mist/pllclk_ez.qip b/sw/synth/platform/pacman/mist/pllclk_ez.qip
new file mode 100644
index 0000000..a6994c4
--- /dev/null
+++ b/sw/synth/platform/pacman/mist/pllclk_ez.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pllclk_ez.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.ppf"]
diff --git a/sw/synth/platform/pacman/mist/pllclk_ez.vhd b/sw/synth/platform/pacman/mist/pllclk_ez.vhd
new file mode 100644
index 0000000..7b64b2d
--- /dev/null
+++ b/sw/synth/platform/pacman/mist/pllclk_ez.vhd
@@ -0,0 +1,495 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pllclk_ez.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 177 11/07/2012 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pllclk_ez IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pllclk_ez;
+
+
+ARCHITECTURE SYN OF pllclk_ez IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC ;
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire9_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire9_bv(0 DOWNTO 0) <= "0";
+	sub_wire9    <= To_stdlogicvector(sub_wire9_bv);
+	sub_wire5    <= sub_wire0(3);
+	sub_wire4    <= sub_wire0(4);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c0    <= sub_wire2;
+	c2    <= sub_wire3;
+	c4    <= sub_wire4;
+	c3    <= sub_wire5;
+	locked    <= sub_wire6;
+	sub_wire7    <= inclk0;
+	sub_wire8    <= sub_wire9(0 DOWNTO 0) & sub_wire7;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 100,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 111,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 25,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 37,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 125,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 74,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 20,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 37,
+		clk3_phase_shift => "0",
+		clk4_divide_by => 27000000,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 18449999,
+		clk4_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pllclk_ez",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire8,
+		clk => sub_wire0,
+		locked => sub_wire6
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "100"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "25"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "125"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "20"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "29.969999"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "39.959999"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "15.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "49.950001"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "18.450001"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "111"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "37"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "74"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "37"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "30.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "16.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "18.45000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pllclk_ez.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "100"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "111"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "37"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "125"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "74"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "37"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "27000000"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "18449999"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/sw/synth/platform/pacman/mist/project_pkg.vhd b/sw/synth/platform/pacman/mist/project_pkg.vhd
new file mode 100644
index 0000000..d323f57
--- /dev/null
+++ b/sw/synth/platform/pacman/mist/project_pkg.vhd
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.pace_pkg.all;
+use work.target_pkg.all;
+use work.video_controller_pkg.all;
+
+package project_pkg is
+
+	--  
+	-- PACE constants which *MUST* be defined
+	--
+	
+  -- Reference clock is 16MHz
+  constant PACE_HAS_PLL						: boolean := true;
+  --constant PACE_HAS_SRAM                    : boolean := true;
+  constant PACE_HAS_SDRAM                   : boolean := false;
+  constant PACE_HAS_FLASH                   : boolean := false;
+  constant PACE_HAS_SERIAL                  : boolean := false;
+  
+  constant PACE_JAMMA	                    : PACEJamma_t := PACE_JAMMA_NONE;
+
+  constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_VGA_800x600_60Hz;
+  constant PACE_CLK0_DIVIDE_BY        		: natural := 5;
+  constant PACE_CLK0_MULTIPLY_BY      		: natural := 3;   -- 16*15/8 = 30MHz
+  constant PACE_CLK1_DIVIDE_BY        		: natural := 5;
+  constant PACE_CLK1_MULTIPLY_BY      		: natural := 4;   -- 16*5/2 = 40MHz
+  constant PACE_VIDEO_H_SCALE         		: integer := 2;
+  constant PACE_VIDEO_V_SCALE         		: integer := 2;
+  constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '1';
+  constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '1';
+
+  constant PACE_VIDEO_BORDER_RGB            : RGB_t := RGB_GREEN;
+
+  constant PACE_HAS_OSD                     : boolean := false;
+  constant PACE_OSD_XPOS                    : natural := 0;
+  constant PACE_OSD_YPOS                    : natural := 0;
+
+        -- Pacman-specific constants
+
+  constant PACMAN_ROM_IN_SRAM               : boolean := false;
+  constant PACMAN_USE_INTERNAL_WRAM         : boolean := true;
+  constant PACMAN_USE_VIDEO_VBLANK          : boolean := true;
+  
+        -- derived
+  constant PACE_HAS_SRAM                    : boolean := PACMAN_ROM_IN_SRAM or 
+                                                 not PACMAN_USE_INTERNAL_WRAM;
+
+  type from_PROJECT_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+  type to_PROJECT_IO_t is record
+    not_used  : std_logic;
+  end record;
+end;
diff --git a/sw/synth/platform/pacman/retroramblings_c3/pacman.qpf b/sw/synth/platform/pacman/retroramblings_c3/pacman.qpf
new file mode 100644
index 0000000..becf671
--- /dev/null
+++ b/sw/synth/platform/pacman/retroramblings_c3/pacman.qpf
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2005 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic       
+# functions, and any output files any of the foregoing           
+# (including device programming or simulation files), and any    
+# associated documentation or information are expressly subject  
+# to the terms and conditions of the Altera Program License      
+# Subscription Agreement, Altera MegaCore Function License       
+# Agreement, or other applicable license agreement, including,   
+# without limitation, that your use is for the sole purpose of   
+# programming logic devices manufactured by Altera and sold by   
+# Altera or its authorized distributors.  Please refer to the    
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "5.0"
+DATE = "19:21:54  August 25, 2005"
+
+
+# Revisions
+
+PROJECT_REVISION = "pacman"
diff --git a/sw/synth/platform/pacman/retroramblings_c3/pacman.qsf b/sw/synth/platform/pacman/retroramblings_c3/pacman.qsf
new file mode 100644
index 0000000..d384d33
--- /dev/null
+++ b/sw/synth/platform/pacman/retroramblings_c3/pacman.qsf
@@ -0,0 +1,178 @@
+# copyright (c) 1991-2005 altera corporation
+# your use of altera corporation's design tools, logic functions 
+# and other software and tools, and its ampp partner logic       
+# functions, and any output files any of the foregoing           
+# (including device programming or simulation files), and any    
+# associated documentation or information are expressly subject  
+# to the terms and conditions of the altera program license      
+# subscription agreement, altera megacore function license       
+# agreement, or other applicable license agreement, including,   
+# without limitation, that your use is for the sole purpose of   
+# programming logic devices manufactured by altera and sold by   
+# altera or its authorized distributors.  please refer to the    
+# applicable agreement for further details.
+
+
+# the default values for assignments are stored in the file
+#		pacman_assignment_defaults.qdf
+# if this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# altera recommends that you do not modify this file. this
+# file is updated automatically by the quartus ii software
+# and any changes you make may be lost or overwritten.
+
+
+# project-wide assignments
+# ========================
+set_global_assignment -name LAST_QUARTUS_VERSION "12.0 SP1"
+
+# pin & location assignments
+# ==========================
+
+# analysis & synthesis assignments
+# ================================
+set_global_assignment -name TOP_LEVEL_ENTITY target_top
+
+# fitter assignments
+# ==================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25Q240C8
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+
+# assembler assignments
+# =====================
+
+set_global_assignment -name SEED 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+
+
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name VHDL_FILE ../../../../src/target/retroramblings_c3/target_top.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/retroramblings_c3/target_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/target/retroramblings_c3/custom_io.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/pace_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/pace_pkg_body.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/stubs/sdram_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller_pkg_body.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/tilemapctl_e.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/bitmapctl_e.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_pkg_body.vhd
+set_global_assignment -name VHDL_FILE project_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/platform_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/pll.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/sprom.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/dpram.vhd
+set_global_assignment -name VHDL_FILE ../../../device/cycloneiii/spram.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/clk_div.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/ps2/ps2kbd_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/ps2/ps2kbd.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/T80se.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/cpu/t80/Z80.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/altera_mem.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_controller.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pengo/tilemapctl.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/spritereg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pengo/spritectl.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/sprite_array.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/video/video_mixer.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/Graphics.VHD
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/InputMapper.VHD
+set_global_assignment -name VHDL_FILE ../../../../src/pace/Inputs.VHD
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/Pacman_Interrupts.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/Pacman_vramMapper.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/platform.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/pacsnd.Vhd
+set_global_assignment -name VHDL_FILE ../../../../src/platform/pacman/sound.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/pace/pace.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/gamecube/gamecube_pkg.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/load_upcounter.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/conversion.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_read2.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_write.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/mfifo.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_bus.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/io/maple/maple_joy.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/toys/led_chaser.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/toys/pwm_chaser.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/toys/pwmout.vhd
+set_global_assignment -name VHDL_FILE ../../../../src/component/sound/sigma_delta_dac.vhd
+set_global_assignment -name QIP_FILE pllclk_ez.qip
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+set_global_assignment -name SIGNALTAP_FILE stp1.stp
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to VGA_HS -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to VGA_VS -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to VGA_HS -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to VGA_VS -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to CLOCK_50 -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to joy1[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to joy1[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to joy1[2] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to joy1[3] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to joy1[4] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to joy1[5] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to joy1[6] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to joy1[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to joy1[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to joy1[2] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to joy1[3] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to joy1[4] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to joy1[5] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to joy1[6] -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=9" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=9" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=48" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=15469" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=31549" -section_id auto_signaltap_0
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/sw/synth/platform/pacman/retroramblings_c3/pllclk_ez.qip b/sw/synth/platform/pacman/retroramblings_c3/pllclk_ez.qip
new file mode 100644
index 0000000..82a306f
--- /dev/null
+++ b/sw/synth/platform/pacman/retroramblings_c3/pllclk_ez.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.0"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pllclk_ez.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pllclk_ez.ppf"]
diff --git a/sw/synth/platform/pacman/retroramblings_c3/pllclk_ez.vhd b/sw/synth/platform/pacman/retroramblings_c3/pllclk_ez.vhd
new file mode 100644
index 0000000..325fdbd
--- /dev/null
+++ b/sw/synth/platform/pacman/retroramblings_c3/pllclk_ez.vhd
@@ -0,0 +1,495 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pllclk_ez.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.0 Build 263 08/02/2012 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pllclk_ez IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pllclk_ez;
+
+
+ARCHITECTURE SYN OF pllclk_ez IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC ;
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire9_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire9_bv(0 DOWNTO 0) <= "0";
+	sub_wire9    <= To_stdlogicvector(sub_wire9_bv);
+	sub_wire5    <= sub_wire0(3);
+	sub_wire4    <= sub_wire0(4);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c0    <= sub_wire2;
+	c2    <= sub_wire3;
+	c4    <= sub_wire4;
+	c3    <= sub_wire5;
+	locked    <= sub_wire6;
+	sub_wire7    <= inclk0;
+	sub_wire8    <= sub_wire9(0 DOWNTO 0) & sub_wire7;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 5,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 3,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 5,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 4,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 25,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 8,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 200,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 109,
+		clk3_phase_shift => "0",
+		clk4_divide_by => 50000000,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 18449999,
+		clk4_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pllclk_ez",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire8,
+		clk => sub_wire0,
+		locked => sub_wire6
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "30.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "16.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "27.250000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "18.450001"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "30.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "16.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "27.25000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "18.45000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pllclk_ez.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "200"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "109"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "50000000"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "18449999"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pllclk_ez_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/sw/synth/platform/pacman/retroramblings_c3/project_pkg.vhd b/sw/synth/platform/pacman/retroramblings_c3/project_pkg.vhd
new file mode 100644
index 0000000..d323f57
--- /dev/null
+++ b/sw/synth/platform/pacman/retroramblings_c3/project_pkg.vhd
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+library work;
+use work.pace_pkg.all;
+use work.target_pkg.all;
+use work.video_controller_pkg.all;
+
+package project_pkg is
+
+	--  
+	-- PACE constants which *MUST* be defined
+	--
+	
+  -- Reference clock is 16MHz
+  constant PACE_HAS_PLL						: boolean := true;
+  --constant PACE_HAS_SRAM                    : boolean := true;
+  constant PACE_HAS_SDRAM                   : boolean := false;
+  constant PACE_HAS_FLASH                   : boolean := false;
+  constant PACE_HAS_SERIAL                  : boolean := false;
+  
+  constant PACE_JAMMA	                    : PACEJamma_t := PACE_JAMMA_NONE;
+
+  constant PACE_VIDEO_CONTROLLER_TYPE       : PACEVideoController_t := PACE_VIDEO_VGA_800x600_60Hz;
+  constant PACE_CLK0_DIVIDE_BY        		: natural := 5;
+  constant PACE_CLK0_MULTIPLY_BY      		: natural := 3;   -- 16*15/8 = 30MHz
+  constant PACE_CLK1_DIVIDE_BY        		: natural := 5;
+  constant PACE_CLK1_MULTIPLY_BY      		: natural := 4;   -- 16*5/2 = 40MHz
+  constant PACE_VIDEO_H_SCALE         		: integer := 2;
+  constant PACE_VIDEO_V_SCALE         		: integer := 2;
+  constant PACE_VIDEO_H_SYNC_POLARITY       : std_logic := '1';
+  constant PACE_VIDEO_V_SYNC_POLARITY       : std_logic := '1';
+
+  constant PACE_VIDEO_BORDER_RGB            : RGB_t := RGB_GREEN;
+
+  constant PACE_HAS_OSD                     : boolean := false;
+  constant PACE_OSD_XPOS                    : natural := 0;
+  constant PACE_OSD_YPOS                    : natural := 0;
+
+        -- Pacman-specific constants
+
+  constant PACMAN_ROM_IN_SRAM               : boolean := false;
+  constant PACMAN_USE_INTERNAL_WRAM         : boolean := true;
+  constant PACMAN_USE_VIDEO_VBLANK          : boolean := true;
+  
+        -- derived
+  constant PACE_HAS_SRAM                    : boolean := PACMAN_ROM_IN_SRAM or 
+                                                 not PACMAN_USE_INTERNAL_WRAM;
+
+  type from_PROJECT_IO_t is record
+    not_used  : std_logic;
+  end record;
+
+  type to_PROJECT_IO_t is record
+    not_used  : std_logic;
+  end record;
+end;
