{"id":627,"date":"2013-08-07T00:25:16","date_gmt":"2013-08-07T00:25:16","guid":{"rendered":"http:\/\/retroramblings.net\/?page_id=627"},"modified":"2020-02-01T15:33:50","modified_gmt":"2020-02-01T15:33:50","slug":"the-zpu-processor","status":"publish","type":"page","link":"https:\/\/retroramblings.net\/?page_id=627","title":{"rendered":"ZPUFlex"},"content":{"rendered":"

The ZPU or Zylin Processing Unit<\/a> is a compact microprocessor architecture suitable for use in FPGA projects. Its main claim to fame is that despite being tiny compared with most 32-bit RISC CPU cores, there is a full GCC toolchain available – in fact the OpenCores page says the ZPU is the world’s smallest 32-bit CPU with GCC toolchain<\/a>.<\/p>\n

Rather than being a specific single processor design, the ZPU is more of a specification which defines a set of instructions (some of which are mandatory, some of which can be emulated), and there are a number of different cores which implement this instruction set.<\/p>\n

Despite the maintainers’ obvious desire to reduce the number of ZPU variants and offer just a few definitive cores, I’ve ended up creating yet another variant, which I’ve come to call ZPUFlex<\/a>.<\/p>\n

ZPUFlex is based on the zpu_small core, but as its name might suggest, adds flexibility.  Compared with the vanilla zpu_small core this version:<\/p>\n