{"id":1854,"date":"2022-03-29T17:44:12","date_gmt":"2022-03-29T17:44:12","guid":{"rendered":"http:\/\/retroramblings.net\/?p=1854"},"modified":"2025-09-30T10:26:00","modified_gmt":"2025-09-30T10:26:00","slug":"jtag-and-tcl-twin-rabbitholes","status":"publish","type":"post","link":"https:\/\/retroramblings.net\/?p=1854","title":{"rendered":"JTAG and Tcl – twin rabbitholes!"},"content":{"rendered":"\n

2022-03-29<\/strong><\/p>\n\n\n\n

I’ve been experimenting with the QMTech Kintex7 board, which provides a huge FPGA for a less huge amount of money. The one thing that prevents my existing projects from running on it without deep changes is the lack of SDRAM, but since I’ve been wanting to get more familiar with the Xilinx ecosystem for a while, this was a good opportunity to dive in.<\/p>\n\n\n\n\n\n\n\n

Firstly, it should be noted that the Kintex 7 XC7K325T part on this board is *not* supported by the free version of Vivado – which means if you want an out-of-the-box experience you need to use ISE. If you’re willing to ride the bleeding edge, then Project X-Ray already has initial support for this chip – so the future of this board with the Open Source toolchain should be very interesting! (See https:\/\/github.com\/kintex-chatter for a collection of works-in-progress.)<\/p>\n\n\n\n

For now, though, I’m going to turn my attention to ISE. The last version released was 14.7, and the WebPack Edition also doesn’t support the XC7K325T – however, Embedded Edition does, and at the time of writing, it’s also free.<\/p>\n\n\n\n

It requires some finessing to make it work on a modern Linux distro – something which can also be said about the older versions of Quartus required for Cyclone II and III support – I’ve been collecting together some information on this subject here: https:\/\/github.com\/robinsonb5\/FPGAToolchainQuirks<\/a><\/p>\n\n\n\n

The last time I had any real exposure to Xilinx devices I was using the venerable “Platform Cable USB”, and surprise no. 1 was the discovery that this device isn’t well supported outside of Xilinx’s own software: OpenOCD doesn’t support it, OpenFPGALoader doesn’t support it, URJTAG has support which it describes as “Slow, experimental – don’t use.”<\/p>\n\n\n\n

There’s an alternative firmware which can be uploaded into the Platform Cable to make it behave like a USB Blaster – but I haven’t yet had any success with this, using either a Platform Cable DLC9, or a Platform Cable II DLC10.<\/p>\n\n\n\n

XC3SProg *does* support the Platform Cable USB, however.<\/p>\n\n\n\n

For the EightThirtyTwo CPU I have a rudimentary Debug interface which works by transmitting 32-bit words over an Intel Virtual JTAG interface, and bridging that to TCP\/IP by way of a Tcl script. I wanted to be able to do the same with a Xilinx chip. Tcl isn’t a necessary part of the equation – simply bridging directly from JTAG to TCP\/IP would be sufficient to use the 832 debugger – however, Tcl does allow some interesting things to be done with Tk (for instance, I have a demo which allows the colour of an FPGA-controlled VGA screen to be set using sliders on a GUI running on the PC.) So Tcl support is filed under “Nice to have”.<\/p>\n\n\n\n

Surprise no. 2 was the discovery that Tcl extensions are *ridiculously* easy to write!<\/p>\n\n\n\n

I started with a copy of the source to the xc3sprog executable, to create a libtcljtag.so shared library, which can be loaded using Tcl’s load command. I set it to build with -fPIC (required to avoid relocation issues when building theshared library) and created a simple class to wrap the JTAG manipulation functions, exposing them as Tcl commands.<\/p>\n\n\n\n

So far the following commands are defined (all under the jtag:: namespace):<\/p>\n\n\n\n