{"id":569,"date":"2013-06-24T19:20:52","date_gmt":"2013-06-24T19:20:52","guid":{"rendered":"http:\/\/retroramblings.net\/?p=569"},"modified":"2013-07-06T11:18:58","modified_gmt":"2013-07-06T11:18:58","slug":"a-new-distraction","status":"publish","type":"post","link":"https:\/\/retroramblings.net\/?p=569","title":{"rendered":"A New Distraction!"},"content":{"rendered":"<p>I have another new toy to distract me from all the things I <em>should<\/em> be doing!<\/p>\n<p><a href=\"http:\/\/retroramblings.net\/wp-content\/uploads\/2013\/06\/Vampire500_InSitu.jpg\"><img loading=\"lazy\" decoding=\"async\" alt=\"Vampire500_InSitu\" src=\"http:\/\/retroramblings.net\/wp-content\/uploads\/2013\/06\/Vampire500_InSitu.jpg\" width=\"686\" height=\"500\" \/><\/a><\/p>\n<p>This is one of <a href=\"http:\/\/www.majsta.com\/\">Majsta&#8217;s<\/a> hand-assembled prototypes of his FPGA accelerator, connected to a spare A500 motherboard that I just happened to have lying around.\u00a0 (I don&#8217;t currently have an A600 to play with, which is why Majsta sent me the less-mature A500 variant of the project).\u00a0 While I&#8217;ve been trying to help with the SDRAM problems his project&#8217;s run into, there&#8217;s only so much I can do without access to the hardware.\u00a0 Well, now I have that access!<\/p>\n<p>The A500 variant of the project&#8217;s not yet as complete as the A600 version, and can&#8217;t yet boot from the TG68 processor, so now begins the fun of testing the various kinds of accesses to the A500 motherboard, and ironing out the glitches.<\/p>\n<p>Because the whole project takes some time to build, while I&#8217;m testing and diagnosing I&#8217;m using a simple state machine to simulate the CPU, which looks like this:<\/p>\n<pre>library ieee;\r\nuse ieee.std_logic_1164.all;\r\nuse ieee.std_logic_unsigned.all;\r\nuse ieee.numeric_std.all;\r\n\r\nentity DummyCPU is\r\n\u00a0\u00a0 \u00a0generic(\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0SR_Read : integer:= 0;\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 --0=&gt;user,\u00a0\u00a0 1=&gt;privileged,\u00a0\u00a0\u00a0\u00a0\u00a0 2=&gt;switchable with CPU(0)\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0VBR_Stackframe : integer:= 0;\u00a0 --0=&gt;no,\u00a0\u00a0\u00a0\u00a0 1=&gt;yes\/extended,\u00a0\u00a0\u00a0 2=&gt;switchable with CPU(0)\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0extAddr_Mode : integer:= 0;\u00a0\u00a0\u00a0 --0=&gt;no,\u00a0\u00a0\u00a0\u00a0 1=&gt;yes,\u00a0\u00a0\u00a0 2=&gt;switchable with CPU(1)\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0MUL_Mode : integer := 0;\u00a0\u00a0 \u00a0\u00a0\u00a0 --0=&gt;16Bit,\u00a0 1=&gt;32Bit,\u00a0 2=&gt;switchable with CPU(1),\u00a0 3=&gt;no MUL, \u00a0\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0DIV_Mode : integer := 0;\u00a0\u00a0 \u00a0\u00a0\u00a0 --0=&gt;16Bit,\u00a0 1=&gt;32Bit,\u00a0 2=&gt;switchable with CPU(1),\u00a0 3=&gt;no DIV, \u00a0\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0BitField : integer := 0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 --0=&gt;no,\u00a0\u00a0\u00a0\u00a0 1=&gt;yes,\u00a0\u00a0\u00a0 2=&gt;switchable with CPU(1) \u00a0\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0);\r\n\u00a0\u00a0 port(clk\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: in std_logic;\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 nReset\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: in std_logic;\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0--low active\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 clkena_in\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: in std_logic:='1';\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 data_in\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: in std_logic_vector(15 downto 0);\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0IPL\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0 \u00a0\u00a0\u00a0 \u00a0: in std_logic_vector(2 downto 0):=\"111\";\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0IPL_autovector\u00a0 \u00a0\u00a0\u00a0 \u00a0: in std_logic:='0';\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0CPU\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: in std_logic_vector(1 downto 0):=\"00\";\u00a0 -- 00-&gt;68000\u00a0 01-&gt;68010\u00a0 11-&gt;68020(only some parts - yet)\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 addr\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: buffer std_logic_vector(31 downto 0);\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 data_write\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: out std_logic_vector(15 downto 0);\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nWr\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: out std_logic;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nUDS, nLDS\u00a0\u00a0 \u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: out std_logic;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0busstate\u00a0\u00a0 \u00a0 \u00a0\u00a0\u00a0 \u00a0 \u00a0\u00a0\u00a0 \u00a0: out std_logic_vector(1 downto 0);\u00a0\u00a0 \u00a0-- 00-&gt; fetch code 10-&gt;read data 11-&gt;write data 01-&gt;no memaccess\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nResetOut\u00a0\u00a0 \u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: out std_logic;\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 FC\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: out std_logic_vector(2 downto 0);\r\n-- for debug\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0skipFetch\u00a0\u00a0 \u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: out std_logic;\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 regin\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0: buffer std_logic_vector(31 downto 0)\r\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 );\r\nend DummyCPU;\r\n\r\narchitecture rtl of DummyCPU is\r\n\r\ntype states is (write1,write2,write3,write4,write5,write6,read1,read2);\r\nsignal state : states := read1;\r\nsignal counter : unsigned(15 downto 0);\r\nsignal temp : std_logic_vector(15 downto 0);\r\n\r\nbegin\r\n\r\nprocess(clk)\r\nbegin\r\n\u00a0\u00a0 \u00a0nResetOut&lt;=nReset;\r\n\u00a0\u00a0 \u00a0if nReset='0' then\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0state&lt;=read1;\r\n\u00a0\u00a0 \u00a0elsif rising_edge(clk) then\r\n\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0case state is\r\n\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0when write1 =&gt;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0data_write&lt;=temp; -- std_logic_vector(counter);\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0addr&lt;=X\"00DFF180\";\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0busstate&lt;=\"11\";\u00a0\u00a0 \u00a0-- Write data\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0state&lt;=write2;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nWR&lt;='0';\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nUDS&lt;='0';\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nLDS&lt;='0';\r\n\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0when write2 =&gt;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0if clkena_in='1' then\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0state&lt;=write3;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0end if;\r\n\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0when write3 =&gt;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0addr&lt;=X\"00BFE201\";\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0data_write&lt;=X\"0003\"; -- Set OVL and LED as output\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nWR&lt;='0';\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nUDS&lt;='1';\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nLDS&lt;='0';\u00a0\u00a0 \u00a0-- Byte write to odd address.\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0state&lt;=write4;\r\n\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0when write4 =&gt;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0if clkena_in='1' then\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0state&lt;=write5;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0end if;\r\n\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0when write5 =&gt;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0addr&lt;=X\"00BFE001\";\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0data_write&lt;=X\"FFFF\";\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0data_write(1)&lt;=temp(6);\u00a0\u00a0 \u00a0-- Echo mouse button status to keyboard LED.\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nWR&lt;='0';\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nUDS&lt;='1';\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nLDS&lt;='0';\u00a0\u00a0 \u00a0-- Byte write to odd address.\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0state&lt;=write6;\r\n\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0when write6 =&gt;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0if clkena_in='1' then\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0state&lt;=read1;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0end if;\r\n\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0when read1 =&gt;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0addr&lt;=X\"00BFE001\";\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0busstate&lt;=\"10\";\u00a0\u00a0 \u00a0-- Read data\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0state&lt;=read2;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nWR&lt;='1';\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nUDS&lt;='1';\u00a0\u00a0 \u00a0-- Byte read from odd address.\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0nLDS&lt;='0';\r\n\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0when read2 =&gt;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0temp&lt;=data_in;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0if clkena_in='1' then\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0state&lt;=write1;\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0end if;\r\n\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0end case;\r\n\u00a0\u00a0 \u00a0end if;\r\nend process;\r\n\r\nend architecture;<\/pre>\n<p>This state machine reads the value of CIA-A PRA and writes the value read to the COLOR0 register, so the colour of the screen changes in response to the mouse or joystick buttons. It also writes the status of the left mouse button to the LED bit, so the keyboard LED lights in response to the mouse button.<\/p>\n<p>Next I shall test reads and writes to Chip RAM and reads from the Kickstart ROM for reliability.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>I have another new toy to distract me from all the things I should be doing! This is one of Majsta&#8217;s hand-assembled prototypes of his FPGA accelerator, connected to a spare A500 motherboard that I just happened to have lying &hellip; <a href=\"https:\/\/retroramblings.net\/?p=569\">Continue reading <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[3,4],"tags":[],"class_list":["post-569","post","type-post","status-publish","format-standard","hentry","category-amiga","category-fpga"],"_links":{"self":[{"href":"https:\/\/retroramblings.net\/index.php?rest_route=\/wp\/v2\/posts\/569","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/retroramblings.net\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/retroramblings.net\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/retroramblings.net\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/retroramblings.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=569"}],"version-history":[{"count":8,"href":"https:\/\/retroramblings.net\/index.php?rest_route=\/wp\/v2\/posts\/569\/revisions"}],"predecessor-version":[{"id":597,"href":"https:\/\/retroramblings.net\/index.php?rest_route=\/wp\/v2\/posts\/569\/revisions\/597"}],"wp:attachment":[{"href":"https:\/\/retroramblings.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=569"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/retroramblings.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=569"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/retroramblings.net\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=569"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}