{"id":719,"date":"2013-12-28T16:43:28","date_gmt":"2013-12-28T16:43:28","guid":{"rendered":"http:\/\/retroramblings.net\/?p=719"},"modified":"2013-12-28T18:48:00","modified_gmt":"2013-12-28T18:48:00","slug":"bringing-up-a-new-board-2","status":"publish","type":"post","link":"https:\/\/retroramblings.net\/?p=719","title":{"rendered":"Bringing up a new board"},"content":{"rendered":"

Part 2: Hello World<\/strong><\/p>\n

Since my last post I’ve received yet another board from Emanuel – another prototype FPGA board with Spartan 6, SDRAM and SSRAM.\u00a0 This one’s a little simpler than the previous board, with no ports other than USB on the board itself, and a daughter card with a VGA connector on it.\u00a0 Unlike the previous board, which had a 2-bits-per-gun resistor ladder DAC, this one has an ADV7123 video DAC chip – the same one used on the DE2 board – which has an impressive 10 bits per gun.\u00a0 That’s good enough to do 24-bit true colour with headroom for calibration tables!<\/p>\n

\"EMS11-BB21\"<\/a><\/p>\n

So, let’s get “Hello World” running on this board.<\/p>\n

I’m going to use the ZPUDemos repository, which I’ve tagged at the appropriate point, so we can check it out like so:<\/p>\n

git clone https:\/\/github.com\/robinsonb5\/ZPUDemos\r\ncd ZPUDemos\r\ngit checkout 20131228_1\r\ngit submodule init\r\ngit submodule update<\/pre>\n
You should now have a clean copy of the repo.<\/p>\n
We need to add the following files<\/p>\n
In HelloWorld\/fpga\/ we need to add a directory for the new board – so:<\/p>\n
mkdir HelloWorld\/fpga\/ems11-bb21<\/pre>\n
Now it’s time to fire up ISE and create a new project.<\/p>\n
Specify \/path\/to\/ZPUDemos\/HelloWorld\/fpga\/ems11-bb21\/ as the path to the new project, and call it “HelloWorld”.\u00a0 ISE will want to create a HelloWorld subdirectory, but that’s unnecessary here.<\/p>\n
Now we need to specify the device, which in this case is family: “Spartan 6”, Device: “XC6SLX45”, Package: “FGG676”.\u00a0 Also set the preferred language to VHDL, then click through to the end of the New Project wizard.<\/p>\n
We need to create a toplevel file for the new board, which will be filed in the “ZPUDemos\/RTL” directory.\u00a0 We also need a .ucf file to specify pin mappings.\u00a0 I have a .ucf file for the board, which has been automatically generated from the schematics – but the signals are all commented out by default, and some signal names need changing since they’re not valid in VHDL.\u00a0 So we’ll take a gradual approach, and enable them bit by bit.\u00a0 The .ucf file will go in ZPUDemos\/Board\/<\/p>\n
For “Hello World” we only actually need two pins defined.\u00a0 We need a clock input, and we need an RS232 serial output.\u00a0 These we can find on pin D14 for a 50MHz clock input, and L18 for the signal called “RXD1(FROM_FPGA)”.\u00a0 We can’t use brackets for VHDL signal names, so we’ll rename that to RXD1_FROM_FPGA.\u00a0 (That’s rxd from the perspective of the attached computer, not the FPGA.\u00a0 That’s why I like the SPI nomenclature – Master In, Slave Out is completely unambiguous regarding direction!)<\/p>\n
So the 50MHz input clock is specified in the .ucf file like so:<\/p>\n
NET \"CLK50\" LOC = \"D14\";\r\nNET \"CLK50\" IOSTANDARD = LVTTL;\r\nNET \"CLK50\" TNM_NET = \"CLK50\" | CLOCK_DEDICATED_ROUTE = FALSE;\r\nTIMESPEC \"TS_CLK50\" = PERIOD \"CLK50\" 20 ns HIGH 50 %;<\/pre>\n
The board has two RS232 interfaces available to the FPGA – both of which are carried over a single USB cable – for now we’ll only define one of them, but we will define all four signals, not just the one required for Hello World:<\/p>\n
NET \"RXD1_FROM_FPGA\" LOC = \"L18\";\r\nNET \"N_CTS1_FROM_FPGA\" LOC = \"K19\";\r\nNET \"N_RTS1_TO_FPGA\" LOC = \"H24\";\r\nNET \"TXD1_TO_FPGA\" LOC = \"F24\";\r\n\r\nNET \"RXD1_FROM_FPGA\" IOSTANDARD = LVTTL;\r\nNET \"N_CTS1_FROM_FPGA\" IOSTANDARD = LVTTL;\r\nNET \"N_RTS1_TO_FPGA\" IOSTANDARD = LVTTL;\r\nNET \"TXD1_TO_FPGA\" IOSTANDARD = LVTTL;<\/pre>\n
The simplified first-approximation toplevel file looks like this:<\/p>\n
-- Toplevel file for EMS11-BB21 board\r\n\r\nlibrary ieee;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nuse IEEE.numeric_std.ALL;\r\n\r\nentity EMS11_BB21Toplevel is\r\nport\r\n(\r\n\u00a0\u00a0 \u00a0CLK50 : in std_logic;\r\n\u00a0\u00a0 \u00a0TXD1_TO_FPGA : in std_logic;\r\n\u00a0\u00a0 \u00a0RXD1_FROM_FPGA : out std_logic;\r\n\u00a0\u00a0 \u00a0N_RTS1_TO_FPGA : in std_logic;\r\n\u00a0\u00a0 \u00a0N_CTS1_FROM_FPGA : out std_logic\r\n);\r\nend entity;\r\n\r\narchitecture rtl of EMS11_BB21Toplevel is\r\n\r\nbegin\r\nN_CTS1_FROM_FPGA<='1';\u00a0 -- safe default since we're not using handshaking.\r\n\r\nproject: entity work.VirtualToplevel\r\n\u00a0\u00a0\u00a0 generic map (\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0sysclk_frequency => 500 -- Sysclk frequency * 10\r\n\u00a0\u00a0 \u00a0)\r\n\u00a0\u00a0 \u00a0port map (\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0clk => CLK50,\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0reset_in => '1',\r\n\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0-- UART\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0rxd => TXD1_TO_FPGA,\r\n\u00a0\u00a0 \u00a0\u00a0\u00a0 \u00a0txd => RXD1_FROM_FPGA\r\n);\r\n\r\nend architecture;<\/pre>\n
So having added the toplevel and the .ucf file to the project, we also need to add the following files:<\/p>\n