The VGA demo demonstrates making use of a simple VGA framebuffer with the ZPU processor.
This project makes use of a simple VGA controller which is integrated with a DMA buffer that links to the SDRAM controller, and supports two bits of dithering to give 6-bit virtual output on the DE1’s 4-bit output, and 8-bit virtual output on the MIST board.
Currently only one hardware register is implemented – the framebuffer base address. This framebuffer is a fixed 640×480 screen with 16-bit (5-6-5) depth. The demo program simply writes an incrementing value into the framebuffer.