The ZPU or Zylin Processing Unit is a compact microprocessor architecture suitable for use in FPGA projects. Its main claim to fame is that despite being tiny compared with most 32-bit RISC CPU cores, there is a full GCC toolchain available – in fact the OpenCores page says the ZPU is the world’s smallest 32-bit CPU with GCC toolchain.

Rather than being a specific single processor design, the ZPU is more of a specification which defines a set of instructions (some of which are mandatory, some of which can be emulated), and there are a number of different cores which implement this instruction set.

Despite the maintainers’ obvious desire to reduce the number of ZPU variants and offer just a few definitive cores, I’ve ended up creating yet another variant, which I’ve come to call ZPUFlex.

ZPUFlex is based on the zpu_small core, but as its name might suggest, adds flexibility.  Compared with the vanilla zpu_small core this version:

  • Moves the dual-port block RAM containing the stack and initial program out of the core itself and instead specifies an interface to the same.  This makes it possible to use more than one ZPU core in a single project, and have each one executing different firmware.
  • Makes the size of the stack / boot ROM selectable through Generics.  Again, this helps if you want to use multiple instances with different sized ROMs in a single project.
  • Includes selectable hardware implementations of enough of the optional instructions that it’s possible to omit the emulation exceptions from the ROM, thus allowing the user to trade resource usage against speed and code size.
  • Can remap the stack to a user-selectable address, leaving the low address space clear for “real” RAM.
  • Is optionally capable of running code from external RAM rather than just the boot ROM, making it possible to bootstrap from SD card or Flash a program too large to fit in the boot ROM.

The ZPU is not a particularly fast CPU – its beauty is in its simplicity and flexibility.  The simplicity of design makes it an ideal candidate for anyone who wants to study and experiment with the operation of a CPU.

On an Altera FPGA, the ZPUFlex takes up roughly 1,000 logic elements when all the bells and whistles are enabled, and a little over half that when cut to the bone.

Full source for the ZPUFlex can be found on my GitHub pages.

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