Part 4 – improving memory performance
Since the last instalment I’ve slightly modified the program run by the TG68, so that instead of simply filling a rectangle with the current colour it mixes it with the colour already there. Quite apart from looking prettier on-screen, this increases the demands on memory access, making for a better testbed for the next stage of the project: caches.
In the current design, when the TG68 wants to access memory, a request signal is raised. Depending on which part of the SDRAM cycle this happens, it can be up to 15 cycles before the controller notices the request, and if the bus is busy it can be 16 cycles more before the request is serviced. Since the processor’s waiting around for this to happen, it makes sense to add a temporary buffer into which a pending write can be placed, so the processor can carry on working. Better yet, since the SDRAM cycle’s already set up for 4-word bursts, if the processor tries to write to an address that will be written during the burst, we can gang the writes up and perform them as one operation.
Likewise, when reading we’re getting four-word bursts from the SDRAM controller, so it makes sense to store all four words, which lets us respond immediately if the processor then asks for another word from the same burst.
There are a couple of complications we have to take care of. Firstly, when writing the processor uses two signals to indicate which of the high and low bytes of the word should be written. This allows byte writes even though the bus is 16-bits wide. The write cache has to store these signals alongside the data to be written.
The other complication, which I haven’t yet attended to, since it doesn’t affect this test project, is that with both read and write caches in use, it’s possible for the read cache to contain stale data. To fix this, I just need to mark the read cache as dirty if it holds data from an address that’s being written to.
The code, as always, for anyone who might be interested, can be downloaded here.