Solving the puzzle…

Exploring audio DACs in simulation – Part 3 – 2021-04-03

Having set up a simplistic testbench in Verilator, I want to be able to use it to evaluate several different DACs. The ones I will be testing are:

  • The simple 1st-order Sigma Delta I included in my last post.
  • A 2nd order DAC found on Github: https://github.com/hamsternz/second_order_sigma_delta_DAC/blob/master/second_order_dac.v – however, I’ve adapted this to halve the input volume by discarding the lowest bit, since second- (and higher) order 1-bit sigma delta DACs are unstable at the extremities of their input range – they require some headroom. Since the Amiga application only requires 15-bit input this is not a problem.
  • A 3rd-order DAC found in Mark Watson’s Atari 800 repository. I’m not sure where it originally came from or what its copyright status is, since it’s not listed in Mark’s otherwise comprehensive list of which license applies to which files. The 3rd order DAC already attenuates the signal to maintain stability so I didn’t need to modify this one, except as detailed below.
  • Finally, the simplest form of my hybrid DAC.
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Let’s “hear it” for Verilator!

Exploring audio DACs in simulation – Part 1 – 2021-03-21

When I was developing EightThirtyTwo I made good use of GHDL, which allowed me to run the CPU’s VHDL code in simulation and output traces of internal signals for viewing in GTKWave.

Now I’ve started exploring Verilator for simulating Verilog code, and it’s safe to say I’m very impressed!

So a little back-story is in order: [Ok, it turns out there’s so much back-story I didn’t actually talk about Verilator – next time, I promise!]

Some years ago I spent some time trying to improve the audio output on Minimig, and encountered some strange counter-intuitive problems. Originally the DAC used by Minimig was a simple 1st-order Sigma Delta DAC. These have pros and cons:

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Selecting & Uploading a ROM

Porting a Core, DeMiSTified – Part 6 – 2021-03-12

When I created a ZPU-based control module for the MSX and PC-Engine cores way back when, I created a menu system which used a tree of static menu structures, in which each elements could be one of several types.

I supported function callbacks, checkmarks, cycles and even sliders. It worked fairly well and the footprint was reasonably small – but it doesn’t lend itself to building a menu dynamically.

In order to build an arbitrary menu from a MiST config string using this system I would need to support memory allocation, which means managing a memory pool, and if the menu ever needs to be re-generated, potentially dealing with fragmentation. Doing any of this without bursting through the self-imposed 12k limit is unlikely to happen!

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Masquerading as MiST

Porting a Core, DeMiSTified – Part 5 – 2021-03-07

I’m not going to go into great depth regarding the substitute controller module which I’m using for this project, since I’ve covered much of that ground in previous posts (see the previous series about the ZPU-based control module, the TG68_MiniSoC project and also EightThirtyTwoDemos) – in all cases I have a soft CPU with a number of memory-mapped hardware registers, and I’m following much the same pattern this time around.

Briefly, I have a UART for serial debugging output, an SPI chip select register which allows one of several SPI channels to be selected, an SPI data transfer register, a simple interrupt controller, PS/2 keyboard and a simple timer in the form of a millisecond counter. I also have a joystick input register, since the controller will be responsible for relaying joystick events into the guest core.

So having created a CPU and peripheral module which we can connect to the guest core, all that remains is porting the firmware, yes?

Well…. no.

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Generalising the Core

Porting a Core, DeMiSTified – Part 4 – 2021-03-03

(Before I start this installment, I should say that I have now released the Chameleon port of the NES core – I’m not going to delay the core just to talk about the process!)

So we have a project file for the MiST version of the core, and we need to create project files for other platforms. My scripts and Makefiles will produce these files, so what I need to do is extract a list of components from the .qsf project file for MiST.

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Managing Project Files

Porting a Core, DeMiSTified – Part 3 – 2021-03-01

When an FPGA core is a self-contained standalone project with only one target board, managing the project from within the FPGA vendor’s IDE works fine. However, once there’s a significant amount of shared code between projects, or you’re building for multiple targets, things get more tedious,

EightThirtyTwoDemos currently has targets for nine different boards, and there are another four within easy reach that I could add if I wished. There are nine demo projects in the repo, so I could have to rebuild as many as 81 projects when something changes. Loading each project, one after another, and rebuilding them manually would be ridiculously inefficient – a better solution is needed.

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A look at MiST’s toplevel

Porting a core, DeMiSTified – Part 2 – 2021-02-25

The goal is to provide an environment in which a MiST core can be included as a submodule, thus porting the core to a new target board without making large-scale changes. To do this, we’re going to need a toplevel for each target board which maps the signals of MiST’s FPGA to board-specific resources.

Let’s take a close look at a MiST core’s toplevel…

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