Experimenting with TG68

Part 12b – a better cache

I’ve *finally* found the subtle bug that was causing my two-way cache to fail.  The symptom was that the boot process would appear to work fine, loading an S Record off the SD card, but having loaded it, the code would fail to start.  It was as though the bootloader was ignoring the S9 record at the end of the firmware file.

After various fruitless attempts to track this down, and to construct artificial testcases to trigger the behaviour, I finally added some serial debugging breadcrumbs to the first-stage bootloader.  From this I found that the final S9 record was being treated as thought it were an S1!

Having discovered that fact, I was able to employ the ever-useful SignalTap, catch the “9” being written to the SREC_TYPE variable, and watch it being read out again.  At this point I finally realized what was going on:  Because that location had been accessed repeatedly, *both* ways of the cache were referencing SREC_TYPE, but the code which updates cached data was only operating on one way or the other – it wasn’t writing to both!

In the end the fix was as simple as removing an “else”.

Having proved that the cache works, the next task is to integrate the write cache, and remove it from the SDRAM controller.  Once that works, I plan to integrate the cache into the Minimig project.

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