Part 1: The Plan!

Having received the ESM-BB10 Spartan 6 board a couple of weeks ago I was naturally keen to see it in action.  Since I only have the free “WebPack” version of Xilinx’s ISE design suite, I can’t use the ChipScope logic analyzer (roughly equivalent to SignalTap, I believe) – so debugging is going to be tricky.  Therefore I’ve taken a methodical, step-by-step approach, testing the various parts of the board one by one.

The ZPUDemos collection is ideal for this purpose, since the projects there range in complexity from a simple “Hello World” that requires no peripherals apart from RS232 serial, to projects that make use of VGA, SDRAM and SD card.Since most of the FPGA boards I’ve played around with so far have been Altera-based, I’m fairly familiar with Quartus, but don’t know much about ISE, so I’ll document some of the things I’ve learned in the process.

So I ought to explain a bit about the structure of the ZPUDemos repository:  The directory structure is as follows:

• ZPUFlex – a submodule, tied to the ZPUFlex repository (check out with “git submodule init” followed by “git submodule update”)
• Board – Board-specific files, currently just containing files relating to clocking for the Minimig and ESM-BB10 board.
• Common_Firmware – library files used by the various projects’ firmware
• TimingConstraints – board-specific .sdc files used by Quartus to constrain timing for SDRAM.  I may move these into the “Board” directory at some point.
• RTL – general-purpose components and peripherals used by the various projects.
  • GeneratedCycloneII – RAMs and Clocks specific to Cyclone II (DE1)
  • GeneratedCycloneIII – RAMs and Clocks specific to Cyclone III (MIST, C3Board, Chameleon)
  • GeneratedCycloneIV – RAMs and Clocks specific to Cyclone IV (Coreboard)
  • Generic – RAMs expressed in a general enough way to build on all targets.
• Apps – standalone programs that can be loaded from SD card or uploaded over RS232

Then the various projects.  The ones I’m interested in for testing the ESM-BB10 are as follows, and in this order:

• HelloWorld – requires nothing more than RS232 output.  Can run from the board’s own clock.
• SDRAM – requires that the SDRAM controller be configured with the correct number of rows and columns.  Requires clock generation to be working, with two copies of the master clock, one slightly phase-shifted.  Ideally needs timing constraints set up.
• VGA – requires working SDRAM, and working BlockRAM-based DMA buffer
• RS232Bootstrap – requires working SDRAM, working DMA, ideally working SD card too.  Can receive projects from “Apps” over RS232, so an ideal testing platform.
• SDBootstrap – similar to RS232 bootstrap, only bootstraps from SD card instead of over RS232.