Learn something new every day…

So while I’m experimenting with FPGA boards I generally upload a design into them at runtime via a USB-Blaster JTAG cable, and only rarely do I store a design permanently in a board’s configuration device.

Some of the boards I use have two separate connectors for the USB Blaster – one for direct programming of the FPGA and the other for Active Serial programming of an EPCS series flash device.  Others have an onboard microcontroller which handle configuration – and then there’s the Vampire 500 board.  This has a single JTAG connector and an EPCS4 configuration device, but no immediately obvious means of programming the EPCS4.

With no direct access to the configuration device, programming has to be done from within the FPGA itself.  It’s easy to find examples or descriptions of programming an EPCS with a NIOS II SoPC component, but as I discovered a short while ago, there are simpler methods:

(Copied-and-pasted here for convenience, and instructions changed to suit the Vampire board…)

  • Open your Quartus project and compile it.
  • Select “File>Convert Programming Files…”.
  • Select “JTAG Indirect Configuration File (.jic)” as type of programming file.
  • Select “EPCS4” in the “Configuration Device” list.
  • By default, it will generate a “output_file.jic” in your project folder. You can modify it in the “File name” field.
  • In the bottom list, select “Flash Loader” and press on the “Add Device…” button on the right.
    • Select Cyclone II and EP2C8, and press “OK”.
  • Now select “Sof Data” and press on the “Add File…” button on the right.
    • Select the .sof file of your project and press “Open”.
  • Press on the “Generate” button.
  • Now, open the Programmer (Tools>Programmer).
  • Select the generated .jic file instead of the .sof file.
  • Tick “Program/Configure” and press “Start”.


4 thoughts on “Learn something new every day…

  1. Yes 🙂 In the process of designing I decided to go maybe non traditional way. In programmer list, on the picture showed, you will notice that FPGA is actually connected to EPCS4 device. So you have done everything correctly. I have tested this number of times and every single time it worked. Why is this so great. You will notice how fast core will be uploaded from EPCS4 to FPGA once programmed. So basically once programmed board will be flashed in milliseconds once is booted. You can play with that device, flash it or maybe best thing you can use rest of cappacity to add boot ROM or something. Another device EPCS16 is larger,faster but it is more complex to design it and maybe needed for more complex designs with Cyclone III or higher. You must admit that this approach is maybe crazy but interesting 🙂 One more thing when you program like this your A500 will freeze and need to restart, this happening only when you program device, when boots from device no problems.

    • It seems like a very sensible approach to me – certainly more sensible than having a second JTAG header on the board. So now I’m curious to know whether the second header, if present, somehow prevents using this method? I’m guessing not, but there’s only one way to find out!

      • Second header JTAG header can be used but this needs some modification in design regarding some specific pins on FPGA, those pins are disabled now. All of this is is explained in Cyclone II handbook but if you look at the their proposals you will notice that I didn’t create everything by the book. I had some my own ideas to simplify everything. When all of this gets interesting is when you using more than one FPGA. If you want I can elaborate more what is done but as long as it works it is not important 🙂

  2. One more thing i forget to say. Last year I was doing DOS executable python based scripts for that and it can be done. What will do detect FPGA over JTAG and upload file to EPCS4. I didn’t have the time to finish it but it can be done.

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