Sigma Delta without Math – Part 2 – 2021-12-04
Last time around I talked about strategies for halftoning graphics, and made the key point that “noise” and “objectionable noise” are not the same thing.
I haven’t yet mentioned, though, the class of dither patterns which has been used most commonly since the advent of the desktop printer – namely Error Diffusion.
Continue readingSigma Delta without Math – Part 1 – 2021-11-10
If, like me, you’ve been curious about the best way to get good quality audio out of an FPGA, but found that all search avenues lead to impenetrable diagrams with lots of arrows, accumulators and terms like [1/z^-1] then this series is for you!
Continue reading2021-11-06
I’ve been porting the VIC20 core from MiST to TC64 recently, and since various people have asked me about the process involved in porting cores I thought I’d document the process this time.
I’ve been recording a series of screencast videos which I’ve published on Patreon, but I may as well include them here, too.
They’re not tutorials as such (since I make no claim that what I’m doing is the best or most correct way!) – they’re more of a video diary – but maybe someone will find them interesting…
I will add to the list of links as new parts are released:
2021-10-19
Out of curiosity I recently tried to build the toolchain for ZPU – and as I rather suspected would happen, it has succumbed to the Half Life of Software, and no longer builds cleanly on up-to-date systems.
[smug mode]In the meantime, I recently succeeded in building the 832 toolchain (832a, 832l, 832d and the 832 VBCC backend) for Amiga, using the Amiga version of VBCC and the Minimig core![/smug mode]
I still have a definite soft spot for ZPU, though.
Continue reading2021-10-02
The DeMiSTify framework has now proved useful in porting a number of retro console and computer cores from the MiST board to the Turbo Chameleon 64, and others have found it useful in porting cores to the DECA board, which I mentioned in my previous post.
However, the jewel in the MiST crown has always been the Atari ST cores: it has two – the original MiST core which was developed side-by-side with the board sharing its name – and also the MiSTery core, an evolution of the project which features a cycle-exact implementation of the CPU and also most of the chipset.
Continue reading2021-09-23
A few months ago I bought a couple of the ridiculously cheap DECA boards from Arrow – they’re sadly sold out now – but $37 bought you a MAX10 FPGA with 50,000 LEs, some DDR3 RAM, i2s audio, an HDMI port, USB and network ports, and a couple of GPIO headers. (It also bought you all the blue LEDs – I highly recommend not looking directly at the board when you power it up for the first time!)
I’m not the only one who’s been interested by this board – a bunch of MiST and MiSTer cores have already been ported to a DECA-based reference platform which involves a MiSTer-style SDRAM module, PS/2 keyboard, DB9 joystick and VGA video on the GPIO headers.
There is now an open-source DDR3 memory controller which has DECA as a main supported target.
And there is a project which caught my attention recently, which turns the DECA board into an external USB2 soundcard.
Yes, you read that correctly.
Naturally I wanted to try this out, so I cloned the repo on my own machine. Hmmm… there seems to be lots of Python involved. I’m not familiar with Python, but by now it’s a well-established, mature language with reliable, well-thought-out packaging and dependency management, right?
Continue reading2021-08-07
A few weeks ago I was helping someone with an FPGA problem, and realised that I take for granted the phenomenally useful tool that is SignalTap. Since the person I was trying to help wasn’t familiar with it, I put together a quick Crash Course video. Initially unlisted, it’s apparently been useful for at least one other person, so I decided to make it public in the hope that others might find it useful too
Maybe I’ll do some more Crash Courses in future…
Writing a new SDRAM controller – part 4 – 2021-08-06
The SDRAM controller I’ve described so far in this series is basically performing well – not quite as well as the one it’s intended to replace – but there’s still one more trick we can use to squeeze out a little more performance…
Continue readingWriting a new SDRAM controller – part 3 – 2021-07-25
In the previous instalments I talked about improving throughput by interleaving read and write transactions to different banks, as well as access patterns I need to avoid and some subtle timing issues which need to be considered.
The challenges remaining to be solved are ensuring that the controller responds in good time to incoming requests on multiple ports, and making the controller run fast enough that it meets timing at the desired speed. For the PC Engine core the desired clock speed is 128MHz
Continue readingWriting a new SDRAM controller – Part 2 – 2021-07-10
Last time I talked about the form of a typical SDRAM read cycle, and how we can improve the overall throughput by interleaving reads to different banks.
The same principle applies to write cycles, too.
Continue reading