Part 2: Saving cycles
2018-03-25
In the first part of this series I covered some basic tidy-ups to the code to make it easier to maintain. Now I’ll look at how we can speed things up.
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2018-03-19
The Megadrive/Genesis core has been plagued from the start with graphical issues that result from the SDRAM controller not responding quickly enough. Over the last few days I’ve finally put some time into understanding the SDRAM controller used by the project and spent some time improving its throughput.
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2018-03-05
I’ve just made available an updated version of the Sega Megadrive / Genesis core for the Turbo Chameleon 64. The only change is to the joystick handling – I’ve untangled the joystick directions and remapped the buttons slightly.
There’s still not a lot of point in using a traditional 1-button C64 joystick with this, but I’ve also fixed a bug in my previous attempt which prevented the CDTV infra-red controller from working. This does now work, and the buttons are mapped as follows:
Play / Pause => Megadrive Start Volume Up => Megadrive A A => Megadrive B B => Megadrive C
I’ve mapped Volume UP to button A simply because it physically feels in the right place. The CDTV pad isn’t super-responsive, so trying to use for serious gameplay is an exercise in frustration, but it does work, and the controllers are readily available from AmigaKit.
The new core can be found here: fpgagen_chameleon_20180305.zip
One of the challenges I’ve faced in the ZPUDemos project is keeping the various targets up to date. When I add a peripheral to – for example – the SDBootstrap SOC, I have to modify each and every target’s project file to match, and it’s very easy to lose track of which ones have been updated and which ones haven’t.
ZPUDemos currently supports no fewer than eight different target boards, and contains eleven different projects – that’s a lot of project files!
In an attempt to make this more manageable, I’ve written some scripts to generate project files automatically, from a list of RTL files, and a board-specific template file. I’ve taken the opportunity to clean up the whole project, too, so the directory structure is more logical. Continue reading
Part 7 – Loading data from SD card.
In this part of the series I’m going to look at the most useful aspect of the control module – using it load data from SD card and pass it to the host core.
To make a meaningful demonstration, the host core needed to be able to do something with the received data, so I’ve pulled in the SDRAM controller and VGA framebuffer from the ZPUDemos project. What I’ve called the “host core”, the part of the project which the ZPU-based control module is supporting, is now capable of displaying a 640x480x16-bit VGA screen from SDRAM, and as such the project is now quite a bit more complicated; however, the only new file needed by the control module itself is spi.vhd which handles communication with the SD card.
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Part 6 – resource sharing
So far we have the control module merging an on-screen display with the underlying host core’s video output, responding to keypresses and running a simple on-screen menu. The largest single addition now will be SD card access, which I will explore in the next part. In this part, however, I’m going to talk about resource sharing.
Some cores, like the test-pattern generator we’ve been using so far or the PC-Engine core, make no use of the keyboard or SD card, so giving sole access to the control module is no problem. If, on the other hand, the underlying core does make use of keyboard and SD card (such as the OneChipMSX core, for instance) we need to have some way of arbitrating for access to these resources. Continue reading
Part 5 – Adding a Menu
Having talked in depth about the hardware in previous parts, in this part I’m going to talk about the software side of things.
I mentioned before that the character ROM contains 128 characters which, from characters 32 upwards, are standard 7-bit ASCII. I’ve added some special characters in the lower 32 character slots, however, which have uses in drawing the OSD. The extra characters are as follows:
For the OneChipMSX and FPGA PC Engine cores I put together a simple, lightweight data-driven menu system, which can be found in CtrlModule/Firmware/menu.[c|h]
Part 4 – Keyboard control
So far we have the control module printing a message to the screen and autonomously sending signals to the underlying core. Now it’s time to make it somewhat interactive!
To do this we need to add Keyboard support. Many FPGA platforms still have support for PS/2 keyboards simply because they’re electrically simple and don’t require much in the way of high speed transceivers or carefully-routed circuits to drive them. Thus the PS/2 keyboard is a de-facto standard for FPGA projects, even to the point that on the MIST platform (which has no PS/2 ports, but does have USB ports) there is a bridge component available which makes the keyboard masquerade as PS/2. This is taken care of in the MIST-specific toplevel file, which allows the main project files to be identical between platforms.
To add keyboard support we need three things: a hardware interface to the PS/2 socket (whether it’s real or emulated!), software to drive that hardware interface, and support for interrupts, so that the CPU doesn’t have to poll the hardware waiting for keystrokes.
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Part 3 – Hello World!
This time round I’ve added the On-screen Display component, and the firmware verifies that it’s working correctly by way of the archetypal “Hello World!” message!
I’ve also added project files for the MIST board, and will add support for a Xilinx-based board in the near future.
The source tree to accompany this part is tagged in the git repo as Step2.
The OSD component itself provides a few hardware registers that can be accessed from software, along with a 512-byte character buffer.
The VHDL interface looks like this:
entity OnScreenDisplay is port( reset_n : in std_logic; clk : in std_logic; -- Video hsync_n : in std_logic; -- Sync inputs from the main core, used to time the vsync_n : in std_logic; -- window and pixel signals and position the OSD. enabled : out std_logic; pixel : out std_logic; window : out std_logic; -- Registers addr : in std_logic_vector(8 downto 0); data_in : in std_logic_vector(15 downto 0); data_out : out std_logic_vector(15 downto 0); reg_wr : in std_logic; char_wr : in std_logic; char_q : out std_logic_vector(7 downto 0) ); end entity;
The readable registers are implemented using simple combinational logic and will thus respond within a single clock, so we don’t bother with any kind of req / ack mechanism here, in the interests of keeping things simple.
Address and data from the CPU are placed on addr and data_in, and reg_wr is brought high to trigger a write to a register, and a char_wr is brought high to trigger a write to the character RAM.
data_out and char_q will output data from registers and character RAM, respectively, based on the addr input. This is a constant connection – no req signal is needed. If reading from the registers triggered some kind of action then we’d need a more complete req/ack mechanism here, but since reads are completely passive we don’t need to worry about it in this case.
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