Don’t assume – measure!

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This is my first blog post in more than eighteen months, and while I’ve not been nearly as active tech-wise as previously, I am still porting cores to the Turbo Chameleon 64 (see https://www.patreon.com/coresforchameleon), and more recently I was kindly offered a prototype of the new SiDi128.

Normally I’d have declined, since most of the new FPGA platforms are far too complex for my tastes – but SiDi128 is oldskool. No Linux subsystem here – instead there’s an ARM microcontroller running a tight baremetal firmware which is an evolution of that used on the MiST, which itself can trace its origins back to the original Minimig. The FPGA is nice and big (nearly five times the size of the one on MiST) and the board has dual independent SDRAMs. In other words, a nice incremental improvement on the MiST without an explosion in complexity.

Slingshot on atari-forum, who is the primary core developer on MiST and SiDi128, had already ported the Minimig core to the new platform, and added support for the dual SDRAMs, placing Chip RAM, Kickstart, and slow RAM in one chip, and fast RAM in the other.

The expectation was that this would yield a nice performance boost – but it didn’t.

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Of ByteBeat, weak linkage and compiler magic

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I recently came across some very interesting one-line programs, which generate some primitive music from simple logic expressions – a genre which has come to be known as “bytebeat”.

Being in need of a pointless-but-fun project requiring little to no concentration, I immediately wanted to play with these programs. Implementing the logic directly in an FPGA would be perfectly possible, but I actually chose not to this time – instead I wanted to compile them for the EightThirtyTwo CPU and run the sound through the four-channel DMA sound “chip” contained in EightThirtyTwoDemos (modeled very much after the Amiga’s beloved Paula chip!).

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Installing Lattice Diamond on Mint 20.3

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I’ve been exploring Yosys / NextPnR / Project Trellis on some Lattice ECP5-based boards recently, and I’ve been very impressed and enthused by what I’ve seen. I do have to admit, though, that it’s not “there” yet, especially when it comes to SystemVerilog and VHDL support through the ghdl-yosys-plugin. Yes, you can develop and compile “real” projects with Yosys and friends, but you do have to keep the toolchain’s limitations in mind and design around them.

For this reason I wanted to install and try the “official” software for ECP5 development, namely Lattice Diamond. This left me with a slight problem in that it’s only available on Windows and Redhat Enterprise Linux 6 or 7, with the software distributed in RPM format.

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Ports, PMODs and Pin Numbering

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2022-05-14

Continuing my experiments with the IceSugar-Pro board, building cores using Yosys and friends, I now have EightThirtyTwoDemos running, using PMODs to provide VGA out, I2S audio out, PS/2 keyboard and mouse, and SD card. (The latter isn’t strictly necessary since the FPGA board already has an SD card slot – but it’s on the underside of the board and impossible to access while the IceSugar-Pro is inserted into the carrier board.)

So how did I go about wiring up the PMODs?

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Triggering a capture

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Coping without Signaltap – Part 2 – 2022-04-26

By the end of part 1 I was able to communicate over JTAG with a design running on the IceSugarPro, remotely control the LEDs on the board and read the contents of a wide register through a FIFO queue.

That’s the barebones of a useful debugging subsystem, but to be truly useful we need the ability to set a trigger condition.

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Coping without SignalTap

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2022-04-19 – Part 1: Establishing communication

If I’m going to find the problem with EightThirtyTwo that’s preventing interrupts from working, I’m going to need some way of observing what’s going on. The CPU works in GHDL Simulation, works on Altera/Intel chips, and works on Xilinx chips so there must be something I’m doing which the Open Source toolchain doesn’t like. (Or I may have stumbled upon an actual bug…)

There are basically three problems to solve here:

  • Capturing the state of internal signals
  • Transporting those signals to the host computer
  • Displaying them in a meaningful and readable format.
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JTAG and Tcl – twin rabbitholes!

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2022-03-29

I’ve been experimenting with the QMTech Kintex7 board, which provides a huge FPGA for a less huge amount of money. The one thing that prevents my existing projects from running on it without deep changes is the lack of SDRAM, but since I’ve been wanting to get more familiar with the Xilinx ecosystem for a while, this was a good opportunity to dive in.

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