Masquerading as MiST

Porting a Core, DeMiSTified – Part 5 – 2021-03-07

I’m not going to go into great depth regarding the substitute controller module which I’m using for this project, since I’ve covered much of that ground in previous posts (see the previous series about the ZPU-based control module, the TG68_MiniSoC project and also EightThirtyTwoDemos) – in all cases I have a soft CPU with a number of memory-mapped hardware registers, and I’m following much the same pattern this time around.

Briefly, I have a UART for serial debugging output, an SPI chip select register which allows one of several SPI channels to be selected, an SPI data transfer register, a simple interrupt controller, PS/2 keyboard and a simple timer in the form of a millisecond counter. I also have a joystick input register, since the controller will be responsible for relaying joystick events into the guest core.

So having created a CPU and peripheral module which we can connect to the guest core, all that remains is porting the firmware, yes?

Well…. no.

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Selecting a Candidate…

Porting a Core, DeMiSTified – Part 1 – 2020-02-24

There are many FPGA cores out there which could be ported to the Turbo Chameleon 64 cartridge. In some cases it’s just a question of somebody doing the legwork, in other cases it gets a little bit more involved – but can we do anything to make the amount of work required more manageable?

Long-time readers will know by now that I don’t ask that kind of question out loud unless I already know that the answer is yes!

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Bug fixes and a new instruction…

The EightThirtyTwo ISA – Part 23 – 2021-01-22

It’s been some time since I’ve made any significant changes to the EightThirtyTwo ISA, CPU or compiler backend, and this is mostly because I’ve been busy using it in real projects.

EightThirtyTwo’s original purpose, apart from the obvious learning exercise, was to be the supporting CPU in the AGA Minimig core for the Turbo Chameleon 64, and it’s performed this function quite nicely: it’s significantly smaller than the secondary TG68 used in the ECS core, and somewhat smaller than the OpenRISC cores that were used in some other Minimig variants, while using fewer memory blocks due to its logic-based register file and reasonably good code-density.

Nevertheless there are always bugs to be fixed and improvements to be made.

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The Totally Unscientific Code Density Competition!

The EightThirtyTwo ISA – Part 22 – 2020-05-04

What better way to celebrate Star Wars Day than with a multi-CPU code density shoot-out?! (Well, OK, most people can probably name a dozen better ways without even trying – but this is how I’m choosing to spend it!)

I was curious to know just how well the code density of EightThirtyTwo code generated by the VBCC backend stacks up against other architectures, so I compiled a fixed codebase, namely the OSD control module from one of the many Minimig variants, targetting 832, m68k, MIPS, OpenRISC, RISC-V ARM, and even i386 and x86-64. The results make for interesting reading…

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Endian matters, linker libraries and constructors.

The EightThirty Two ISA – Part 20 – 2020-04-03

I’m continuing to make gradual improvements to the EightThirtyTwo toolchain, and over the last few days I’ve given my attention to linker libraries, and endian issues.

While I initially intended EightThirtyTwo to be a big endian CPU, it occurred to me early on that I could make endian-ness configurable with a generic parameter. This I did, and having set that “littleendian” parameter to “true” for testing, I never actually changed it back, so all my testing over the last few months has actually been in little endian mode!

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Mitigating Hazards

The EightThirtyTwo ISA – Part 17 – 2020-02-16

I was looking today at ways of improving the throughput of the EightThirtyTwo CPU. The design as it stands is very simple, and didn’t make any attempt to perform result forwarding or instruction fusing. These are both strategies for improving the performance of certain constructs, and I wasn’t sure which of these two techniques I should use.

In brief, without either mechanism implemented, when the CPU encounters code such as:

    li 0
mr r0

it has to wait until the first instruction has finished writing to the tmp register before moving its new contents into the pipeline, and only then finally writing it to r0.

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