Coping without SignalTap – Part 3 – 2022-04-28
I’ve found the bug which was preventing interrupts from working with the EightThirtyTwo CPU, at least in the EightThirtyTwoDemos projects…
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Monthly Archives: April 2022
Triggering a capture
Coping without Signaltap – Part 2 – 2022-04-26
By the end of part 1 I was able to communicate over JTAG with a design running on the IceSugarPro, remotely control the LEDs on the board and read the contents of a wide register through a FIFO queue.
That’s the barebones of a useful debugging subsystem, but to be truly useful we need the ability to set a trigger condition.
Continue readingCoping without SignalTap
2022-04-19 – Part 1: Establishing communication
If I’m going to find the problem with EightThirtyTwo that’s preventing interrupts from working, I’m going to need some way of observing what’s going on. The CPU works in GHDL Simulation, works on Altera/Intel chips, and works on Xilinx chips so there must be something I’m doing which the Open Source toolchain doesn’t like. (Or I may have stumbled upon an actual bug…)
There are basically three problems to solve here:
- Capturing the state of internal signals
- Transporting those signals to the host computer
- Displaying them in a meaningful and readable format.
Exploring Yosys/Trellis/NextPnR for Lattice ECP5
2022-04-18
I’ve been tinkering with the IceSugarPro board recently, which is a nice little SO-DIMM form factor FPGA board containing a Lattice ECP5 FPGA. It’s the successor to the earlier IceSugar board which contained a Lattice iCE40UP5k: despite not having an iCE40 series chip, the IceSugarPro retains the name!
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