Achieving 24-bit colour on a 15-bit device – 2021-12-31

[I found this unfinished post in a dusty corner of my drafts folder, and decided that tonight was the night to finish it!]

While I’m sitting through the all-too-familiar wait while Quartus builds a core, I wanted to write a few words about dithering and how I approached the problem of doing 24-bit colour video output on a platform which has only 15 bits of colour resolution on its VGA port.

The video DAC on the Turbo Chameleon 64 has just 5 bits per colour gun which means we can output 32 different levels each of red, green and blue for a total range of 32,768 colours. This is fine for the ECS Minimig core, since the original Amiga has only 4 bits per gun, for a total of 4,096 colours – but the AGA chipset doubles this colour depth to 8 bits per gun, full 24-bit output – so some compromises will be needed.

Sigma Delta without Math – Part 1 – 2021-11-10

If, like me, you’ve been curious about the best way to get good quality audio out of an FPGA, but found that all search avenues lead to impenetrable diagrams with lots of arrows, accumulators and terms like [1/z^-1] then this series is for you!

2021-11-06

I’ve been porting the VIC20 core from MiST to TC64 recently, and since various people have asked me about the process involved in porting cores I thought I’d document the process this time.

I’ve been recording a series of screencast videos which I’ve published on Patreon, but I may as well include them here, too.

They’re not tutorials as such (since I make no claim that what I’m doing is the best or most correct way!) – they’re more of a video diary – but maybe someone will find them interesting…

I will add to the list of links as new parts are released:

• Part 1 – getting the core to build: https://www.youtube.com/watch?v=UZZ-rEvCUUQ
• Part 2 – getting the core to actually work (including a brief foray into the world of timing constraints!): https://www.youtube.com/watch?v=xhDtlOlDnLY
• Part 3 – building for V2 hardware as well as V1, and making sure we haven’t broken the MiST build: https://www.youtube.com/watch?v=a0f3noUQdx8
• Part 4 – disk images – and updating the disk module with a more up-to-date version: https://www.youtube.com/watch?v=dbCn792M-Gk
• Part 5 – handling the C64 keyboard: https://www.youtube.com/watch?v=CWiwvXzGxDc
• Part 6 – adding support for external IEC devices: https://youtu.be/dci3jBvhN6c
• Part 7 – Houston, we have a problem: https://www.youtube.com/watch?v=gbOsg0yr-MY
• Part 8 – Finally solved the V2 problem: https://www.youtube.com/watch?v=06iMXWutxDA

2021-10-02

The DeMiSTify framework has now proved useful in porting a number of retro console and computer cores from the MiST board to the Turbo Chameleon 64, and others have found it useful in porting cores to the DECA board, which I mentioned in my previous post.

However, the jewel in the MiST crown has always been the Atari ST cores: it has two – the original MiST core which was developed side-by-side with the board sharing its name – and also the MiSTery core, an evolution of the project which features a cycle-exact implementation of the CPU and also most of the chipset.

2021-08-07

A few weeks ago I was helping someone with an FPGA problem, and realised that I take for granted the phenomenally useful tool that is SignalTap. Since the person I was trying to help wasn’t familiar with it, I put together a quick Crash Course video. Initially unlisted, it’s apparently been useful for at least one other person, so I decided to make it public in the hope that others might find it useful too

Maybe I’ll do some more Crash Courses in future…

Writing a new SDRAM controller – part 4 – 2021-08-06

The SDRAM controller I’ve described so far in this series is basically performing well – not quite as well as the one it’s intended to replace – but there’s still one more trick we can use to squeeze out a little more performance…

Writing a new SDRAM controller – part 3 – 2021-07-25

In the previous instalments I talked about improving throughput by interleaving read and write transactions to different banks, as well as access patterns I need to avoid and some subtle timing issues which need to be considered.

The challenges remaining to be solved are ensuring that the controller responds in good time to incoming requests on multiple ports, and making the controller run fast enough that it meets timing at the desired speed. For the PC Engine core the desired clock speed is 128MHz