2020-03-13

Long story short: I’ve just spent way too much debugging a problem that turned out simply to be an SDRAM chip’s CKE line not connected in the toplevel design file!

Porting an arcade core to the Turbo Chameleon 64 – Part 2 – 2020-03-06

For the Chameleon64 port of Rampage I needed some way of showing an On-Screen Display. While the core doesn’t have many options to worry about, I did want to be able to display a “Loading” message and an “Error” message if loading the ROM failed.

There are several different ways we could approach this, but as you’ll recall from part 1, we’re very short of block RAM for this project, so minimising block RAM usage will be my priority.

Tunneling debugging information over JTAG – 2020-03-04

One of my primary platforms for FPGA tinkering is the Turbo Chameleon 64 cartridge – which comes in two flavours: the original V1 hardware which features a Cyclone III FPGA and the V2 hardware which has a very similar Cyclone 10LP FPGA (basically the same thing in a newer package).

While this cartridge is intended as an expansion for the venerable Commodore 64 8-bit computer from the 1980s, it can nonetheless run other more general-purpose cores, so most of my projects have Chameleon64 targets. The one downside of this hardware is the lack of general purpose IOs. It has no built-in serial port, and nowhere really convenient to attach a USB-serial dongle either. It’s possible to misuse the IEC port for this purpose, but then I need to remember to disable it before distributing a finished core (I doubt a 1541 disk drive would appreciate having RS232 data spewed at it). There’s also a USB debugging protocol built into the cartridge, which I haven’t yet explored – mostly because so many of my projects can be built for multiple platforms, I’m reluctant to put a large amount of effort into supporting features only available on one of them.

I discovered the other day, however, that it’s possible to tunnel a UART-style connection over JTAG.