So I’m still, in between tinkering with FPGAs, trying to settle upon a Linux distro for desktop use. I still keep coming back to Mint Mate edition despite the annoyances I’ve found with the latest version, and having installed both an SSD and some extra RAM in the machine I’m about to migrate to, I figured I’d better run some tests. The Ubuntu (and thus Mint) live install contains Memtest86+ so I booted from USB, selected the test and watched the machine lock up half way through the very first test.
The solution to my problem was to install memtest86+ using apt, then remove it again. The removal doesn’t remove the meta files, so provided there’s an image of the correct name in /boot it remains in the grub menu. Therefore, one can download a non-broken binary, copy it to /boot, run grub-update and *now* the RAM test actually works.
One side-effect, however, is that the grub setup installed by the USB live system when installing Linux is somewhat different from what you get when you subsequently run grub-update from the installed-and-running system – I had to edit some config files to get the menu back..
If, like me, you’ve been curious about the best way to get good quality audio out of an FPGA, but found that all search avenues lead to impenetrable diagrams with lots of arrows, accumulators and terms like [1/z^-1] then this series is for you!
Out of curiosity I recently tried to build the toolchain for ZPU – and as I rather suspected would happen, it has succumbed to the Half Life of Software, and no longer builds cleanly on up-to-date systems.
[smug mode]In the meantime, I recently succeeded in building the 832 toolchain (832a, 832l, 832d and the 832 VBCC backend) for Amiga, using the Amiga version of VBCC and the Minimig core![/smug mode]
I still have a definite soft spot for ZPU, though.
The DeMiSTify framework has now proved useful in porting a number of retro console and computer cores from the MiST board to the Turbo Chameleon 64, and others have found it useful in porting cores to the DECA board, which I mentioned in my previous post.
However, the jewel in the MiST crown has always been the Atari ST cores: it has two – the original MiST core which was developed side-by-side with the board sharing its name – and also the MiSTery core, an evolution of the project which features a cycle-exact implementation of the CPU and also most of the chipset.
A few months ago I bought a couple of the ridiculously cheap DECA boards from Arrow – they’re sadly sold out now – but $37 bought you a MAX10 FPGA with 50,000 LEs, some DDR3 RAM, i2s audio, an HDMI port, USB and network ports, and a couple of GPIO headers. (It also bought you all the blue LEDs – I highly recommend not looking directly at the board when you power it up for the first time!)
I’m not the only one who’s been interested by this board – a bunch of MiST and MiSTer cores have already been ported to a DECA-based reference platform which involves a MiSTer-style SDRAM module, PS/2 keyboard, DB9 joystick and VGA video on the GPIO headers.
Naturally I wanted to try this out, so I cloned the repo on my own machine. Hmmm… there seems to be lots of Python involved. I’m not familiar with Python, but by now it’s a well-established, mature language with reliable, well-thought-out packaging and dependency management, right?
A few weeks ago I was helping someone with an FPGA problem, and realised that I take for granted the phenomenally useful tool that is SignalTap. Since the person I was trying to help wasn’t familiar with it, I put together a quick Crash Course video. Initially unlisted, it’s apparently been useful for at least one other person, so I decided to make it public in the hope that others might find it useful too
Writing a new SDRAM controller – part 4 – 2021-08-06
The SDRAM controller I’ve described so far in this series is basically performing well – not quite as well as the one it’s intended to replace – but there’s still one more trick we can use to squeeze out a little more performance…
Writing a new SDRAM controller – part 3 – 2021-07-25
In the previous instalments I talked about improving throughput by interleaving read and write transactions to different banks, as well as access patterns I need to avoid and some subtle timing issues which need to be considered.
The challenges remaining to be solved are ensuring that the controller responds in good time to incoming requests on multiple ports, and making the controller run fast enough that it meets timing at the desired speed. For the PC Engine core the desired clock speed is 128MHz