Edit: Future me, nearly 10 years later, says don’t bother attempting these steps unless you really have no alternative. My comment below about guides found on the net quickly becoming obsolete now applies to this post!

If you’re using Ubuntu or a derivative, then the arm-none-eabi-… toolchain is now in the repos, so can easily be installed with apt, and there’s even an m68k gcc cross compiler too.

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To build the OSD firmware for the Minimig projects, a cross-compilation environment is needed. Configuring GCC for this task can be an arcane process, and aspects tend to change from time to time, so guides found on the net quickly become obsolete. For instance, guides recommending the target “arm-elf” will fail with the latest GCC. Instead we need to use the target “arm-none-eabi”.

Here’s how I built a toolchain for building both M68K (Chameleon Minimig port) and ARM (Original Minimig and MiST) versions of the firmware:
Continue reading →

Following on from the addition of the Two Way Cache in my last post, I’ve made some more speed improvements to the Chameleon 64’s Minimig core.

Firstly, I’ve added a single-word write buffer, which means when the CPU writes to Fast RAM it doesn’t have to wait for the write to complete.  Provided completing the write takes priority over any potential reads from the same address, and the Cache is updated to reflect the new data, then the CPU can continue merrily processing.

Secondly, I’ve added a second access slot to the SDRAM controller, which means in many cases the wait for RAM service is reduced from a worst-case 24 cycles to 17 cycles.  The downside is that because RAM operations between the two access slots overlap, they can’t be to the same RAM bank.  For this reason I’ve remapped the RAM so that bank 0 contains Chip RAM, Slow RAM, Kickstart ROM and OSD RAM, leaving banks 1-3 free for Fast RAM.  Chip RAM and Kickstart ROM accesses can thus now overlap with Fast RAM accesses.

Finally, I’ve simplified the TG68 wrapper so that it no longer uses the enaWRreg signal to synchronize the CPU to the Amiga’s 28MHz clock.

Between them these changes give an average speed increase of about 65%. Continue reading →

In my last post I said I was going to integrate the write cache into my two-way cache *before* adding it to the Minimig core – but I got impatient!

Continue reading →

One thing I’ve always found annoying when working with DB9s is that the staggered pins makes them incompatible with matrix board.  The simplest solution has always been to just put the DB9 on the end of a cable, and either solder the cable directly to the board, or use a box header, which has parallel rows of pins.

A few days ago I was hit with a flash of inspiration – and now I can’t believe I didn’t think of this solution sooner! Continue reading →

I’ve recently pushed some changed to the TG68MiniSOC Github repo at https://github.com/robinsonb5/TG68_MiniSOC.  Changes this time round include:

• increasing the system clock frequency to 133MHz.  In order to do this I had to add some wait states to the processor, but the increase in RAM bandwidth makes it worthwhile.
• Adding some more robust filtering to the PS/2 clock signals.  At the faster clock speed I was finding that the mouse and keyboard were misbehaving – it appeared as though there were spurious clock edges causing the receiver to get a bit or two out of sync with the keyboard and mouse.  After trying various tweaks to the PS/2 module’s parameters with no success, I tried running the PS/2 clock signals through the debouncer I mentioned in the post about latching power circuits – and that seems to work like a charm.
• Since two of the target platforms have 32 meg of RAM, and since I now have a Platform Specific register the firmware can read to query how much RAM is present, I’ve moved the base address of the hardware registers.  Previously they were at 0x800000, which is 8 megabytes into the address space.  This works out nicely on the DE1 which only has 8 meg of RAM, but on the Chameleon and CIII board the base address needs to be above 32 meg.  So I’ve changed it to 0x80000000 – or 2GB.  Chances are I’m not going to encounter an FPGA dev board with more than 2 gig of RAM! Continue reading →

I found the source of my Minimig-core problems – one was a misrouting of the SD-card’s chip select signal, and the other was interference from the Action Replay module, which isn’t usable with this version of the core anyway, so I’ve simply disabled it.

The core itself now runs very nicely on the C3 board, with the same basic feature set as the Chameleon core:  On top of the normal Minimig feature set, thanks to the efforts of Tobias Gubener it supports 68020-compatible soft processor, and up to 8 meg of Fast RAM.  My own tweaks to the OSD firmware added support for WinUAE-style HDFs and direct SD card access as well as some other minor tweaks.

There are plenty of further tweaks to be made and problems to solve, but after the frustrations of trying to get it working a few days ago, it’s nice to be able to play some Amiga games on it today!

Here’s Syndicate (courtesy of WHDLoad)

And the workbench from my old A4000, running from an SD card partition.

(The original was DblNTSC.  Interesting that PAL Hi Res should look good on a widescreen monitor!)

Full source and bitstream files for the core are available for download here.